Static information storage and retrieval – Read/write circuit – Bad bit
Patent
2000-02-29
2000-12-12
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, G11C 2900
Patent
active
061607452
ABSTRACT:
A semiconductor storage device contains a row redundancy cell array in which redundancy cells are arranged in connection with redundancy word lines respectively and a memory cell array in which memory cells are arranged in connection with word lines respectively. In a normal operation mode, the word lines are sequentially activated in response to input addresses, so that stored information is read out from each of the memory cells of the memory cell array. If an input address coincides with a defective word line address designating a word line being connected with a defective memory cell within the memory cell array, a redundancy word line is selectively activated as a replacement of the word line which is inhibited from being activated, so that stored information is read out from each of the redundancy cells connected with the redundancy word line. In a burn-in test mode, the redundancy word lines and word lines are collectively activated and are subjected to stress, so that a burn-in test is performed on the redundancy cells and memory cells collectively. Thus, it is possible to reduce the time required for the burn-in test in manufacture. In a defectiveness test mode, the redundancy word lines are sequentially activated and are subjected to stress, so that a defectiveness test is performed to check each of the redundancy cells in quality.
REFERENCES:
patent: 5396124 (1995-03-01), Sawada et al.
patent: 5623448 (1997-04-01), Koelling
Le Vu A.
NEC Corporation
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