Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2002-12-16

2004-10-12

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S189020

Reexamination Certificate

active

06804155

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-279741, filed on Sep. 25, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, and particularly to a semiconductor storage device having an improved redundancy structure for compensating for a defective data line.
2. Description of the Related Art
In recent years, highly integrated semiconductor storage devices employ a redundancy technique of replacing a defective cell with a redundancy cell, in general. Particularly, hybrid DRAMs (Dynamic Random Access Memory) employ a technique of dynamically switching connection of data lines relative to data input/output lines (Namekawa T. et al., “Dynamically shift-switched data line redundancy suitable for DRAM macro with wide data bus”, 1999 Symposium on VLSI Circuits, Digest of Papers, PP. 149-152).
FIG. 13
is a view schematically showing a hybrid DRAM disclosed in the publication described above. As shown in
FIG. 13
, the array region
10
of the DRAM includes a plurality of memory cell array blocks
11
, in each of which a plurality of memory cells are arrayed. Each of the memory cell array blocks
11
is combined with a shift switch block
12
and connection block
13
to form a block unit
15
.
A (k: k is a natural number)-number of data input/output lines (IO lines)
21
are connected to the array region
10
. In the array region
10
, a k-number of common internal data lines (RWD lines)
23
are disposed in common to the plurality of memory cell array blocks
11
. The RWD lines
23
are respectively formed integrally with the IO lines
21
.
On the other hand, in each of the plurality of memory cell array blocks
11
, a (k+2)-number of individual internal data lines (DQ lines)
25
are disposed. Of them, a k-number of DQ lines
25
are connected to the k-number of RWD lines
23
through the shift switch block
12
and connection block
13
.
When data in the memory cells is read, the data is transmitted from the DQ lines
25
through the shift switch block
12
and connection block
13
to the RWD lines
23
, and then is outputted to the IO lines
21
.
This hierarchical structure of data lines is adopted for the following reasons. (1) With an increase in operation frequency required to hybrid DRAMs, it has become necessary to operate in smaller blocks. (2) Since multi-layered interconnection lines have become usable, it is easy to arrange hierarchical structures. (3) Since redundancy can be accomplished in every block unit, it is possible to increase the yield with the same number of spare array portions (an increase in remedy efficiency).
In the DRAM shown in
FIG. 13
, one of the many block units
15
is selected in operation. The DQ lines
25
in each of the block units
15
have redundancy, and are selectively connected to the RWD lines
23
disposed outside the block unit
15
. The selective connection for administering the redundancy function is performed by the connection block
13
and shift switch block
12
. The shift switch block
12
connects the RWD lines
23
and DQ lines
25
to each other, while avoiding defective DQ lines
25
, on the basis of defect information stored in an internal ROM.
The necessary number of IO lines
21
is K, and the number of RWD lines
23
disposed is also K. The DQ lines
25
include two redundancy DQ lines relative to the IO lines
21
and RWD lines
23
, and thus the number of them is k+2.
The shift switch block
12
is designed to connect the RWD lines
23
respectively to the corresponding left side DQ lines
25
in the memory cell array block
11
, when the redundancy function is not used (see the lowermost block unit
15
in FIG.
13
). Accordingly, in the memory cell array block
11
, portions corresponding to two DQ lines on the right side are used as spare portions for redundancy, as indicated with a reference symbol
16
.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor storage device comprising:
an array region including a plurality of memory cell array blocks, in each of which a plurality of memory cells are arrayed, the array region being connected to a (k: k is a natural number)-number of data input/output lines;
a (k+m: m is a natural number)-number of common internal data lines provided in common to the plurality of memory cell array blocks;
a (k+m+n: n is a natural number)-number of individual internal data lines provided to each of the plurality of memory cell array blocks;
an individual line connection circuit for data line redundancy configured to respectively connect a (k+m)-number of the (k+m+n)-number of individual internal data lines to the (k+m)-number of common internal data lines, in accordance with a first defect information signal; and
a common line connection circuit for data line redundancy configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.
According to a second aspect of the present invention, there is provided a semiconductor storage device comprising:
an array region including a plurality of memory cell array blocks, in each of which a plurality of memory cells are arrayed, the array region being connected to a (k: k is a natural number)-number of data input/output lines;
a (k+m: m is a natural number)-number of common internal data lines provided in common to the plurality of memory cell array blocks;
a (k+m)-number of individual internal data lines provided to each of the plurality of memory cell array blocks;
an individual line connection circuit for data line redundancy configured to respectively connect a (k to k+m)-number of the (k+m)-number of individual internal data lines to a (k to k+m)-number of the (k+m)-number of common internal data lines, in accordance with a first defect information signal; and
a common line connection circuit for data line redundancy configured to respectively connect a k-number of the (k to k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.
According to a third aspect of the present invention, there is provided a semiconductor storage device comprising:
an array region including a plurality of memory cell array blocks, in each of which a plurality of memory cells are arrayed, the array region being connected to a (k: k is a natural number)-number of data input/output lines;
a (k+m: m is a natural number)-number of common internal data lines provided in common to the plurality of memory cell array blocks;
a (k+n: n is a natural number)-number of individual internal data lines provided to each of the plurality of memory cell array blocks;
a k-number of intermediate connection lines provided between the common internal data lines and the individual internal data lines, to each of the plurality of memory cell array blocks;
an individual line connection circuit for data line redundancy configured to respectively connect a k-number of the (k+n)-number of individual internal data lines to the k-number of intermediate connection lines, in accordance with a first defect information signal;
a first common line connection circuit for data line redundancy configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal; and
a second common line connection circuit for data line redundancy configured to respectively connect the k-number of common internal data lines to the k-number of intermediate connection lines, in accordance with the second defect information signal.
According to a fourth aspect of the presen

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