Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-10-09
2004-12-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189011, C365S230010, C365S230080
Reexamination Certificate
active
06834020
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor memory device in which the memory cell array is made up from memory cells which are the same as a DRAM (dynamic random access memory), and moreover which, when seen from the outside of the semiconductor memory device, operates with the same specifications as a general-purpose SRAM (static RAM). In particular, the present invention relates to a semiconductor memory device which is suitable for incorporation into a portable instrument, as represented by a portable telephone or PHS (personal handyphone system) or the like.
BACKGROUND ART
SRAMs and DRAMs are typical representatives of semiconductor memory devices which are capable of random access. When compared with a DRAM, generally an SRAM is high speed, and if it is supplied with power source and merely an address is input, it is possible for change of this address to be detected, and for sequential circuits in the interior to operate so as to perform reading and writing. Since in this manner an SRAM, operates only by being provided with a simple input signal waveform, as compared with a DRAM, therefore it is possible to simplify the structure of the circuitry which generates this type of input signal waveform.
Furthermore, since with an SRAM no refresh is required for maintaining the data which is stored in the memory cells as is the case with a DRAM, therefore, since no refresh is necessary, along with its operation being simple, it also has the merit that the electrical current for maintaining the data in the standby state is small. Owing to these facts, SRAMs are widely used for many applications. However, since generally an SRAM needs six transistors for each memory cell, if a great capacity is anticipated, the chip size becomes undesirably great as compared to a DRAM, and there is also the shortcoming that the price itself inevitably becomes high as compared to a DRAM.
On the other hand, for a DRAM, because the address is divided into two portions, the row address and the column address, which must be supplied separately, because a RAS (row address strobe)/CAS (column address strobe) becomes necessary as a signal for determining the input timings of these addresses, because it is necessary to refresh the memory cells periodically, and the like, therefore the timing control inevitably becomes more complicated as compared with an SRAM, moreover, extra circuitry and so on for refresh control becomes necessary.
Furthermore with a DRAM there is also the problem that, due to the fact that refresh for the memory cells becomes necessary even when there is no access from the outside, the consumption of electrical current becomes undesirably great. However, since the memory cells of a DRAM can be made up from one capacitor and one transistor each, therefore there is no need to increase the chip size, and it is comparatively easy to count upon increase in capacity. Accordingly, if it is a question of manufacturing semiconductor memory devices of the same capacity, a DRAM is cheaper than an SRAM.
By the way, as semiconductor memory devices which are to be employed in portable instruments of which representative types are the portable telephone and the like, up till the present, SRAMs are the main type used. This is because only simple functions have been incorporated in portable telephones up until now and therefore high capacity semiconductor memory devices have not been required until the present, because in comparison with DRAMs the operation of SRAMs is simple as far as the points of timing control and the like are concerned, because SRAMs are well adapted for portable telephones and the like in which it is desired to extend the continuous speech time period and the continuous standby receive time period as much as possible since their standby current is small and therefore their power consumption is low, and the like.
Nevertheless, nowadays, portable telephones which are endowed with very rich functionality are becoming progressively more popular, and functions are being implemented such as sending and receiving electronic mail, or, by accessing various sites, obtaining urban information such as data about restaurants in the vicinity and the like. Moreover, with the most recent portable telephones, functions such as display of simplified contents of home pages accessed on web servers upon the internet are also imminently to be provided, and it is also being assumed that in the near future it will become possible freely to access home pages and the like upon the internet in the same manner as with a current desktop type personal computer.
In order to implement these kinds of functions, it is useless only to perform simple text display as with old style portable telephones, and a graphic display becomes indispensable in order to present diverse multimedia information to the user. For this, the requirement has arisen for large quantities of data which have been received from a public network or the like to be temporarily stored in a semiconductor memory device within a portable telephone. In other words, for semiconductor memory devices which are to be fitted to portable instruments from now on, it is considered that having large capacity like a DRAM is an essential condition. However, since it is an absolute condition for a portable instrument that it should be small in size and light in weight, it is necessary to avoid increase in size and in weight of the instrument as a whole, even while increasing the capacity of the semiconductor memory device.
Although as described above an SRAM is desirable as a semiconductor memory device to be fitted to a portable instrument when the convenience of application and power consumption are considered, a DRAM comes to be desirable when viewed from the aspect of increasing capacity. In other words, it may be the that from now on semiconductor memory devices which employ the individual merits of SRAMs and of DRAMs will be most suitable for application to future portable instruments. As this type of semiconductor memory device, ones which are termed “pseudo-SRAMs” have already been contemplated which, while utilizing memory cells which are the same as those employed in DRAMs, have specifications almost identical to those of SRAMs, when seen from the outside.
With a pseudo-SRAM, when supplying the address, it is not necessary to separate it into a row address and a column address as with a DRAM, and furthermore timing signals such as RAS and CAS for implementing this separation are not required either. With a pseudo-SRAM, just as with a general-purpose SRAM, it is acceptable to supply the address only once, and to perform reading/writing by taking in the address internally upon trigger by a chip enable signal which is equivalent to a clock signal for a semiconductor memory device of the clock signal synchronized type.
Of course a pseudo-SRAM is not limited to having absolute compatibility with a general-purpose SRAM; many of them are equipped with refresh control terminals for controlling refresh of the memory cells from the outside, so that it is necessary to control refresh from the exterior of the pseudo-SRAM. In this manner, many pseudo-SRAMs are not so easy to operate as compared with SRAMs, and there is the defect that it becomes necessary to provide extra circuitry for refresh control. Due to this fact, as is introduced below, it has also come to be contemplated to manage without controlling the refresh of a pseudo-SRAM from the outside, and to provide a pseudo-SRAM which is made so that it can be operated with a specification which is exactly the same as that of a general-purpose SRAM. However various defects are present with this type of pseudo-SRAM as well, as will be described below.
First, as a first related art, the semiconductor memory device which has been disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 4-243087 is proposed. With this related art, the pseudo-SRAM itself has no refresh timer, but rather it is arranged for a timer to be provided externally to the pseudo-SRAM. And an OE (o
Inaba Hideo
Nakagawa Atsushi
Takahashi Hiroyuki
Choate Hall & Stewart
Elms Richard
Luu Pho M.
NEC Electronics Corporation
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