Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2001-11-15

2003-07-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S210130, C365S189090

Reexamination Certificate

active

06600684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor storage device to achieve simplification of the screening of defective memory cells in probing tests.
2. Description of Related Art
FIG. 7
is a figure showing in summary an example of the configuration of the principal parts of dynamic RAM (hereafter called “DRAM”) comprising a sense amp.
The DRAM shown in
FIG. 7
comprises a first and second memory cell array (MCBLKl and MCBLKr), and one sense amp
10
.
The two memory cell arrays (MCBLKl and MCBLKr) and the sense amp
10
are connected by a bit line pair comprising two bit lines, indicated by BL and /BL.
In these DRAM memory cell arrays MCBLKl and MCBLKr, numerous word lines intersect with this bit line pair (BL and /BL), and memory cells are connected to these intersections.
In
FIG. 7
, four word lines (WLlm, WLln, WLrm and WLrn), and a first through a fourth memory cell (
12
,
14
,
16
and
18
), are shown.
The sense amp
10
is connected to a sense amp driving line SAen to activate the sense amp
10
.
A first and second transistor T
1
and T
2
are provided between the sense amp
10
and the memory cell array MCBLKl. The gate electrodes of these transistors (T
1
and T
2
) are connected to a transfer gate control line TGl. The channel of the transistor T
1
is provided on the bit line BL, and the channel of the transistor T
2
is provided on the bit line /BL.
Between the sense amp
10
and the memory cell array MCBLKr are provided a third and fourth transistor T
3
and T
4
. The gate electrodes of these transistors (T
3
and T
4
) are connected to a transfer gate control line TGr. The channel of the transistor T
3
is provided on the bit line BL, and the channel of the transistor T
4
is provided on the bit line /BL.
First to third bit line equalizer circuits (
20
,
22
and
24
), including equalizer lines (EQMl, EQMr and EQS), are connected to BL and /BL.
Between BL or /BL, and the data buses DB or /DB, are provided a fifth and sixth transistor (T
5
and T
6
) which control these connections.
A column select line CL is connected to the gates of these transistors (T
5
and T
6
).
FIG. 8
is a figure showing an example of the configuration of a conventional semiconductor storage device, and is used to explain signal outputs of signal lines the names of which appear in
FIG. 7
(TGl, TGr, EQMl, EQMr, EQS).
The signal output circuit shown in
FIG. 8
comprises first, second and third NOT gates (
26
,
28
and
30
), series-connected in order, which take the output voltage level from the memory cell select signal line BSl which selects the memory cell as the output voltage level of the equalizer line EQMl; fourth, fifth and sixth NOT gates (
32
,
34
and
36
), series-connected in order, which take the output voltage level from the memory cell select signal line BSr as the output voltage level of the equalizer line EQMr; a circuit in which are series-connected a first NAND gate
38
and a seventh NOT gate
40
, in this order, which takes the output voltage level from the memory cell select signal lines (BSl and BSr), after passing through the first and fourth NOT gates
26
and
32
respectively, as the output voltage level of the equalizer line EQS; a first transfer gate control line control unit
44
, comprising seventh through 14th transistors (T
7
, T
8
, T
9
, T
10
, T
11
, T
12
, T
13
, T
14
) and an eighth NOT gate
42
, which takes the output voltage level from the memory cell select signal line BSl as the output voltage level of the transfer gate control line TGl; and, a second transfer gate control line control unit
48
, comprising 15th through 22nd transistors (T
15
, T
16
, T
17
, T
18
, T
19
, T
20
, T
21
, T
22
) and a ninth NOT gate
46
, which takes the output voltage level from the memory cell select signal line BSr as the output voltage level of the transfer gate control line TGr.
In
FIG. 8
,
50
and
52
are first and second high-potential voltage output units, which output high voltages (Vcc+Vt+&agr; (where Vcc is the power supply voltage, Vt is a threshold voltage, and &agr;>0)), constantly input from outside, to the first and second transfer gate control line control units.
The first transfer gate control line control unit
44
is connected to the connection point of the NOT gates
26
and
28
, to the output points of the NOT gates
28
and
34
, and to the output point of the first high-voltage output unit
50
. The second transfer gate control line control unit
48
is connected to the connection point of the NOT gates
32
and
34
, to the output points of the NOT gates
34
and
28
, and to the output point of the second high-voltage output unit
52
.
Next, the operation during data readout (zero (0) readout) of the DRAM shown in FIG.
7
and
FIG. 8
is explained.
FIG. 9
is an operating waveform diagram employed in this explanation, indicating the operating waveforms during zero (0) readout from memory cells.
At time t
0
(initial state), both of the above two DRAM memory cell arrays (MCBLKl and MCBLKr) are in the unselected state, and the signal levels of the memory cell select signal lines (BSl and BSr), which select the memory cell for data readout, are both at the low logical level, that is, the “low” state (this state corresponds to a binary “0”, and hereafter is denoted “L”).
From
FIG. 8
, the levels of the equalizer signals output at this time by the equalizer lines (EQMl, EQMr and EQS) are at the logical high level, that is, the “high” state (this state corresponds to a binary “1”, and is hereafter denoted “H”), and each of the bit lines BL and /BL is precharged to the (½)Vcc level (where Vcc is the power supply voltage).
At time t
1
, the signal level of the memory cell select signal line BSl which controls the selected memory cell array MCBLKl changes from the “L” state to the “H” state. This is accompanied by a change in the level of the equalizer signal output from the equalizer lines (EQMl and EQS) from the “H” state to the “L” state.
Hence equalization of the bit lines BL and /BL of the selected memory cell array MCBLKl stops, and so each of the bit lines enters a floating state while being maintained at a potential of (½)Vcc.
Also at this time, the level of the equalization signal output from the equalizer line (EQMr) goes to the “H” state, and equalization of the bit lines BL and /BL of the unselected memory cell array MCBLKr is maintained.
Then, at time t
2
, the output voltage from the transfer gate control line TGl between the selected memory cell array MCBLKl and the sense amp
10
becomes Vcc+Vt+&agr; (where Vt is a threshold value, and &agr;>0).
Further, the transfer gate control line TGr between the unselected memory cell array MCBLKr and the sense amp
10
goes to GND level (for a reason explained below).
Hence the gates of the transistors (T
1
and T
2
) are turned on, and the line between the selected memory cell array MCBLKl and the sense amp
10
becomes conducting. On the other hand, the gates of the transistors T
3
and T
4
are turned off, and the line between the unselected memory cell array MCBLKr and the sense amp
10
is in the non-conducting state.
Next, at time t
3
, one of the word lines (here, assumed to be WLlm) is selected, and the output voltage from this word line (WLlm) goes to the level Vcc+Vt+&agr; (where Vt is a threshold value, and &agr;>0) (word line voltage increase).
At time t
4
, the information written to the memory cell (here, shown by 12) selected by the selected word line (WLlm) is output as a potential difference &Dgr;V to the bit line (here BL). At this time, the voltage of the bit line /BL is at the (½)Vcc level.
Then, at time t
5
, the sense amp enable signal output from the sense amp driving line SAen changes from the “L” state to the “H” state, and in response the sense amp
10
is activated.
Through the sensitivity amplification action of the activated sense amp
10
, the potential of the bit line BL is pulled up to Vcc, and the potential of the bit line /BL is lowered to

Affiliated with

Also associated with

Rating

Semiconductor storage device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor storage device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor storage device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3044021