Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2001-04-19

2003-03-18

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S177000, C365S230050

Reexamination Certificate

active

06535417

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device having an SRAM (Static Random Access Memory) type memory cell. More specifically, this invention relates to a semiconductor storage device which improves resistance to a soft error.
BACKGROUND OF THE INVENTION
In recent years, as the electronic equipments have become light, thin and small, a demand for speeding up functions of the equipments has been strengthened. It is now indispensable to mount a microcomputer to such electric equipments, and it is essential to mount a high-speed memory with large capacity to the microcomputer. Moreover, since personal computers have spread quickly and have required high performance, a large capacity cache memory is required for realizing higher-speed process. Namely, a CPU requires high speed and large capacity as for RAM used when a control program or the like is executed.
DRAM (Dynamic RAM) and SRAM are generally used as the RAM. SRAM is normally used as the above-mentioned cache memory which requires processing to be done at a high-speed. High-resistance load type SRAM composed of four transistors and two high-resistance elements and CMOS type SRAM composed of six transistors are known. Particularly the CMOS type SRAM has high reliability because a leak current at the time of holding the data is very small. At present the CMOS type SRAM is most commonly used.
FIG. 20
is a circuit diagram of a memory cell of the conventional CMOS type SRAM. Only a circuit portion for holding memory is shown. That is, an access-use MOS transistor for reading and writing a memory state is omitted. As shown in this figure, the memory cell can be represented by two inverters INV
1
and INV
2
whose input terminals and output terminals are connected with each other complementarily.
FIG. 21
shows the internal circuit of the inverters INV
1
and INV
2
. That is, this figure shows the CMOS in verter circuit. As shown in
FIG. 21
, both the inverters INV
1
and INV
2
are composed of one PMOS transistor PM
1
and one NMOS transistor NM
1
, respectively. Source of the PMOS transistor PM
1
is connected to a power-supply line V
DD
, and source of the NMOS transistor NM
1
is connected to a ground line GND. Drains of both the transistors are connected to each other. The node of these drains work as an output terminal OUT. Gates of both the transistors are connected to each other. The node of these gates work as an input terminal IN. Namely, a so-called CMOS structure, in which the PMOS transistor PM
1
is a load transistor and NMOS transistor NM
1
is a drive transistor, realizes the in verter function.
Operation of the CMOS in verter circuit shown in
FIG. 21
will be explained below. When an electric potential at a high logical level (hereafter, “H”), namely, potential V
DD
is applied to the input terminal IN, the PMOS transistor PM
1
is brought in to OFF state, and NMOS transistor NM
1
is brought into ON state.
As a result, the output terminal OUT is electrically connected to the ground line via the NMOS transistor NM
1
, and its electric potential becomes an electric potential at a low logical level (hereafter, “L”), namely, a GND potential. On the contrary, when an electric potential with logical level “L”, namely, a GND potential is applied to the input terminal IN, the PMOS transistor PM
1
is brought in to ON state, and the NMOS transistor NM
1
is brought in to OFF state. Resultantly, the output terminal OUT is electrically connected to the power-supply line via the PMOS transistor PM
1
, and its electric potential becomes an electric potential with logical level “H”, namely, V
DD
potential. In such a manner, the CMOS inverter circuit holds a relationship that input and output logics are complementary.
Next, the conventional memory cell shown in
FIG. 20
will be explained blow. The input terminal of the inverter INV
1
and the output terminal of the inverter INV
2
are connected with each other, and the output terminal of the inverter INV
1
and the input terminal of the inverter INV
2
are connected with each other. Accordingly, storage nodes NA and NB in the drawing hold a complementary relationship.
For example, if the storage node NA is in a state of an electric potential with logical level “H”, the storage node NB is in a state of an electric potential with logical level “L” so as to be stable. Further, on the contrary, if the memory node NA is in a state of an electric potential with logical level “L”, the storage node NB is in a state of an electric potential with logical level “H” so as to be stable. The memory cell composed of the inverters has two different and stable logical states according to the “H” or “L” state of the two memory nodes NA and NB. The logical states are held as storage data of 1 bit.
A semiconductor storage device which is composed of the CMOS inverter circuit is very stable, and resistance to noises has not become a problem. However, in the case of the above-mentioned memory with large capacity in which a lot of memory cells are integrated, since an area of the memory cell per 1 bit becomes very small, the memory is exposed to radioactive rays with ionization characteristic so as to be influenced by generated electric charges. Namely, the radioactive rays are emitted so that the storage state of the memory cell becomes unstable, and the possibility of occurrence of malfunction such as inversion of storage data becomes high.
This phenomenon is called as a soft error, the radioactive rays with ionization characteristic are generated from &agr;-rays emitted from the package material or the wiring material. Particularly, the soft error occurs more easily as a power-supply voltage becomes lower. For this reason, in a semiconductor storage device which is driven by a low power-supply in recent years, an important theme is how to increase the resistance to the soft error.
Various semiconductor storage devices are known in which a capacity value of the storage nodes is in creased thereby preventing the in version of storage data due to the emission of &agr;-rays. For example, according to “a semiconductor memory device” disclosed in Japanese Patent Application Laid-Open No. 9-270469, a thin active region intervenes between a storage node (namely, a connecting portion between a gate of a load transistor and a gate of a driving transistor composing a CMOS inverter circuit) and a semiconductor substrate so that a capacitor is formed, and thus a capacity value of the storage node portion is in creased.
Meanwhile, a non-volatile semiconductor storage devices composed of a SRAM memory cell, an access-use transistor and some capacitors are also known. The capacity value of the storage node portion becomes an important problem also in these non-volatile semiconductor storage device.
According to this non-volatile semiconductor storage device, an electric potential is determined by dividing capacity of many capacitors so that writing is executed, and reading at the time when the power-supply is ON is executed according to a relationship in the capacity value of the capacitors connected to the storage node. For this reason, it is difficult to adequately design the capacitors. Therefore, in “a semiconductor non-volatile memory device” disclosed in Japanese Patent Application Laid-Open No. 62-33392, in stead of capacitors, a gate of the MOS transistor having a floating gate is connected to a storage node of a SRAM memory cell so that a non-volatile memory section is constituted, and the number of capacitors is decreased.
However, according to a demand for larger capacity and higher integration of the semiconductor storage device, it is necessary to make components of the memory cell fine. For this reason, a capacity value of the storage node portion becomes smaller, and thus a soft error occurs more easily.
In order to cope with the above problem, the capacity value of the storage node portion is in creased in the prior memory cell in “the semiconductor memory device” disclosed in Japanese Patent Application Laid-Open No. 9-270469. As a result, a specifi

Affiliated with

Also associated with

Rating

Semiconductor storage device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor storage device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor storage device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3020563