Semiconductor storage device

Static information storage and retrieval – Read/write circuit – Particular write circuit

Reexamination Certificate

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C365S230050, C365S154000, C365S203000, C365S230060

Reexamination Certificate

active

07889576

ABSTRACT:
This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, and a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage. Further, the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data.

REFERENCES:
patent: 6292388 (2001-09-01), Camarota
patent: 7161868 (2007-01-01), Morishima
patent: 2002/0163824 (2002-11-01), Athanassiadis
patent: 2005-025863 (2005-01-01), None

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