Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2010-02-03

2011-11-08

Pham, Thanh V (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29255

Reexamination Certificate

active

08053842

ABSTRACT:
It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a Loadless 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.

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