Semiconductor storage device

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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Details

C714S048000

Reexamination Certificate

active

07729157

ABSTRACT:
A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An error correction circuit corrects any error in retained data in the memory cells sensed by the sense amplifier. A plate line control circuit controls the timing for switching a potential of the plate line to a ground potential, based on absence or presence of error correction by the error correction circuit.

REFERENCES:
patent: 6477096 (2002-11-01), Inoue
patent: 6822890 (2004-11-01), Torjussen et al.
patent: 7123501 (2006-10-01), Noda
patent: 2005-135488 (2005-05-01), None
patent: 2006-228291 (2006-08-01), None
patent: 2007-080343 (2007-03-01), None

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