Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2006-10-27

2008-12-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

07460420

ABSTRACT:
The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an address comparison circuit compares a predecoded signal, output by a predecoder, with the defective predecoded signals PDRA, output by the redundant predecoders. In the case of a 2-bit predecoding system, the address comparison circuit compares the predecoded signal PRA with the defective predecoded signal PDRA using four bits in order to compare the row address signal RA with the defective row address signal DRA using groups of two bits.

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patent: 2001093292 (2001-04-01), None
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ULSI Dram Technology.

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