Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2002-05-09
2003-07-08
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S154000, C365S230050
Reexamination Certificate
active
06590802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory cell structure of a semiconductor storage apparatus having an SRAM (Static RAM) memory cell.
2. Description of the Background Art
In recent years, it has been greatly demanded that the weights, thicknesses and sizes of electronic apparatuses should be reduced and the functions of the same apparatuses should be implemented at a high speed. Nowadays, it is essential that a microcomputer should be mounted on such electronic apparatuses. In the structure of the microcomputer, it is required that a memory having a large capacity and a high speed should be mounted. Moreover, it has been required that the capacity of a cache memory should be increased in order to implement a processing more quickly with the rapid spread and high performance of a personal computer. In other words, it has been necessary to increase the speed and capacity of an RAM to be used by a CPU during execution of a control program or the like.
While a DRAM (Dynamic RAM) and an SRAM are generally used for the RAM, the SRAM is usually used in a portion in which a processing is to be carried out at a high speed, for example, the cache memory. As the structure of a memory cell, there have been known an SRAM of a high resistance load type which is constituted by four transistors and two high resistance elements and an SRAM of a CMOS type which is constituted by six transistors. In particular, the SRAM of the CMOS type has a high reliability and is a present mainstream because of a very small leakage current during data hold.
In the memory cell, generally, a reduction in an element area implies the realization of an increase in a speed as well as a reduction in the size of a memory cell array. Conventionally, various layouts have been proposed for the memory cell structure in order to implement an operation of the SRAM to be carried out at a higher speed.
For example, according to “Semiconductor Storage Apparatus” disclosed in Japanese Patent Application Laid-Open No. 10-178110 (1998), a boundary line of a P well region and an N well region where an inverter constituting a memory cell is formed is arranged in parallel with a bit line so that a shape of a diffusion region in the P well region or the N well region and a shape of a cross connecting portion of two inverters can be simplified without a bent portion, resulting in a reduction in a cell area.
FIGS. 22 and 23
are views illustrating a layout structure of the “Semiconductor Storage Apparatus” disclosed in the Japanese Patent Application Laid-Open No. 10-178110 (1998) as seen on a plane. In particular,
FIG. 22
shows a lower part including a diffusion region formed on a semiconductor substrate surface, a polycrystalline silicon film formed on an upper surface of the diffusion region and a first metal wiring layer formed on a first layer, and
FIG. 23
shows an upper part including second and third metal wiring layers formed on second and third layers provided on an upper surface of the lower part.
As shown in
FIG. 22
, an N well region including PMOS transistors P
101
and P
102
is provided on a center of a memory cell, and a P well region including NMOS transistors N
101
and N
103
and a P well region including NMOS transistors N
102
and N
104
are provided on both sides thereof.
The PMOS transistors P
101
and P
102
and the NMOS transistors N
101
and N
102
are mutually cross connected to constitute a CMOS inverter, that is, a flip-flop circuit, and the NMOS transistors N
103
and N
104
correspond to access gates (transfer gates).
As shown in
FIG. 23
, moreover, bit lines BL and {overscore (BL)} are separately formed as the second metal wiring layers and each of them is connected to one of semiconductor terminals of each of the access gate MOS transistors N
103
and N
104
provided thereunder. Moreover, a power line Vdd is formed as the second metal wiring layer in parallel with the bit line in a central part between the bit lines BL and {overscore (BL)}, and is connected to one of semiconductor terminals (source—drain regions) of each of the PMOS transistors P
101
and P
102
provided thereunder. Furthermore, a word line WL is formed as the third metal wiring layer in a direction orthogonal to the bit lines BL and {overscore (BL)} and is connected to gates of the NMOS transistors N
103
and N
104
provided thereunder. Moreover, a grounding conductor GND is formed as two third metal wiring layers in parallel with both sides of the word line WL.
Since the memory cell is formed in such a layout, an N-type diffusion region in the P well region provided with the MOS transistors N
101
and N
103
and an N-type diffusion region provided with the MOS transistors N
102
and N
104
can be formed rectilinearly in parallel with the bit lines BL and {overscore (BL)}. Thus, it is possible to prevent a wasteful region from being generated.
Moreover, a length of a cell in a transverse direction, that is, a length in a direction of the word line WL is relatively greater than a length in a longitudinal direction, that is, lengths of the bit lines BL and {overscore (BL)}. Therefore, a layout of a sense amplifier to be connected to the bit lines BL and {overscore (BL)} can easily be obtained, and furthermore, the number of cells to be connected to one word line can be decreased and a cell current flowing during reading, that is, a consumed power can be reduced.
While the memory cell of the SRAM is an example of a so-called 1-port SRAM, a multiprocessor technique has recently been introduced as one of means for implementing an increase in the speed of a computer and it has been required that a plurality of CPUs should share one memory area. More specifically, various layouts have been proposed for a 2-port SRAM in which access can be given from two ports to one memory cell.
According to “Storage Cell” disclosed in Japanese Patent Application Laid-Open No. 07-7089 (1995), for example, a second port is provided symmetrically with a first port and is simultaneously formed together with the first port on the same layer so that a structure of a 2-port SRAM is implemented.
FIG. 24
shows a layout of the “Storage Cell” disclosed in the Japanese Patent Application Laid-Open No. 07-7089 (1995).
In
FIG. 24
, PMOS transistors P
201
and P
202
and NMOS transistors N
201
a
, N
202
a
, N
201
b
and N
202
b
are mutually cross connected to constitute a CMOS inverter, that is, a flip-flop circuit, and NMOS transistors NA, NB, NA
2
and NB
2
correspond to access gates (transfer gates).
More specifically, in
FIG. 24
, the NMOS transistors NA and NB can give access from one of ports through a word line WL
1
and the NMOS transistors NA
2
and NB
2
can give access from the other port through a word line WL
2
.
In a layout of a conventional 1-port SRAM memory cell having a 6-transistor structure, there has been a problem in that a wiring capacity of a bit line is large because of an increase in a length in a direction of a bit line and an access time becomes long because of an increase in a line capacity. Moreover, the directions of an access transistor and a driver transistor are different from each other. Therefore, there has been a problem in that it is hard to carry out optimization to have a desirable dimension and to maintain a margin for a variation in manufacture due to mask misalignment.
Referring to the SRAM memory cell having the 6-transistor structure, the “Semiconductor Storage Apparatus” disclosed in the Japanese Patent Application Laid-Open No. 10-178110 (1998) proposing a layout structure having a small length in a direction of a bit line solves the problems for the 1-port SRAM. The same contents have also been disclosed in Japanese Patent Application Laid-Open No. 2001-28401.
In the “Semiconductor Storage Apparatus”, however, a 2-port SRAM generally comprising two sets of access gates and a driving type MOS transistor has not solved the problems described above. Moreover, the “Storage Cell” disclosed in the Japanese Patent Application Laid-Open No. 07-7089 (1995) has descr
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Phung Anh
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