Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-05-29
2004-06-15
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S229000, C365S233500
Reexamination Certificate
active
06751144
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor memory device in which a memory cell array is constructed of the same memory cells as DRAM (dynamic random access memory), and moreover which when viewed from outside the semiconductor memory device, operates with the same specifications as SRAM (static RAM). In particular, the present invention relates to a semiconductor memory device which is compatible with SRAM in which a write enable signal for determining the write timing for a memory cell is supplied asynchronously relative to a write address.
BACKGROUND ART
SRAM and DRAM are the most representative examples of semiconductor memory devices to which random access is possible. In comparison with DRAM, SRAM is generally faster, and provided a power source is supplied and an address is input, the internal sequential circuit will operate so as to detect any address transitions, and perform reading and writing. In this manner, because SRAM is operated simply by provision of an input signal waveform which is simple in comparison with DRAM, the construction of the circuit for generating the input signal waveform can also be simplified.
Furthermore, because SRAM does not require a refresh for continued retention of data stored in the memory cells as DRAM does, SRAM offers the advantages that handling is easy, and moreover because a refresh is unnecessary, the data retention current in standby mode is very small. For the above reasons, SRAM is widely used in a variety of applications. However, because SRAM typically requires six transistors for each memory cell, the chip size is always larger than for DRAM, and the cost of SRAM is also higher than for DRAM.
In contrast, DRAM suffers from a more complex timing control than SRAM, in that an address needs to be split in two and provided as a separate row address and column address, and a RAS (row address strobe) signal and a CAS (column address strobe) signal are required as signals for defining the latch timing of these addresses, and a control circuit for regular refresh of the memory cells is required.
Furthermore, DRAM suffers from the problem that even when there is no access from externally, the current consumption is large due to the requirement to conduct a refresh of the memory cells. Having said that, a memory cell of a DRAM can be constructed from a single transistor and a single capacitor, and so a shift to mass storage with a small chip size is relatively easy. Consequently, in constructing semiconductor memory devices of identical storage volume, DRAM will be cheaper than SRAM.
Up until now, SRAM has been the mainstream semiconductor memory device used in portable apparatus such as portable telephones. The reasons for this include the fact that up until now portable telephones have been provided with only simple functions and so large storage semiconductor memory devices have been unnecessary, the fact that SRAM is simpler to handle than DRAM in terms of timing control and the like, and the fact that SRAM has only a small standby current and offers low power consumption and so is more suitable for portable telephones and the like in which extending continuous talk time and continuous standby time is a priority.
However recently, portable telephones which offer a huge number of functions have started appearing, and functions such as the ability to send and receive email, or the ability to access various sites and obtain, for example, general information about local restaurants are now a reality. Moreover, in the most recent portable telephones, functions to enable access to web servers on the internet and the subsequent display of simplified versions of the content of home pages have appeared, and it is envisaged that in the future, access to internet home pages and the like in the same manner as conventional desktop type personal computers will be possible.
In order to realize such functions, the type of simple text display used on conventional portable telephones will be insufficient, and graphic displays for providing a variety of multimedia information to the user will be essential. This will require the temporary storage of large amounts of data received from a public network or the like in semiconductor memory devices housed inside the portable telephone. That is, it is thought that mass storage such as that provided by DRAM will be a necessity for the semiconductor memory devices used in future portable telephones. Moreover, because small size and light weight are two essential conditions for portable apparatus, even if the storage capacity of the semiconductor memory devices used is increased, any increases in size or weight of the apparatus must be avoided.
As described above, consideration of ease of handling and power consumption would suggest SRAM as the preferred semiconductor memory device for use in portable apparatus, but from the viewpoint of mass storage DRAM is preferable. That is, it can be said that for future portable apparatus, a semiconductor memory device which incorporates the advantages of SRAM and DRAM is ideal. An example of such a semiconductor memory device known as pseudo SRAM, which uses the same memory cells as those used by DRAM but which has almost the same specifications as SRAM when viewed from externally, has already been proposed.
Pseudo SRAM does not require addresses to be provided as a separate row address and column address as is the case with DRAM, and furthermore timing signals for these such as RAS and CAS are also unnecessary. Hence with pseudo SRAM, an address is provided at a single time, in the same manner as for standard SRAM, and a chip enable signal corresponding with the clock of a clock synchronous type semiconductor memory device is used as a trigger for latch of an address and the performing of reading or writing.
However, pseudo SRAM is not completely compatible with standard SRAM, and most pseudo SRAM is equipped with a refresh control terminal for controlling the refresh of the memory cells from externally, and the control of the refresh must be controlled from outside the pseudo SRAM. Consequently, in comparison with SRAM, most pseudo SRAM is not particularly easy to handle, and suffer from requiring an extra circuit for refresh control. As a result, pseudo SRAM in which external control of the refresh is unnecessary and which is operated with exactly the same specifications as standard SRAM is also under consideration, as described below. However, as described below, this type of pseudo SRAM also suffers from several drawbacks.
As a first background art example there are the semiconductor memory devices disclosed in Japanese Unexamined Patent Application, First Publication No. Sho-61-5495 and Japanese Unexamined Patent Application, First Publication No. Sho-62-188096. A semiconductor memory device of the former application incorporates an integrated refresh timer for timing the refresh interval, and at the point where a time equivalent to the refresh interval has elapsed, a refresh start request is generated, and following completion of the amplification operation of a bit line pair during a read operation, the word line corresponding to the refresh address is activated and self refresh is performed. By so doing, the need for controlling the refresh of the memory cells from outside the semiconductor memory device disappears.
Furthermore the semiconductor memory device of the latter application specifically discloses a detailed construction for an operation timing control circuit required for realizing the semiconductor memory device of the former application, and in effect is the same semiconductor memory device as that disclosed in the former application.
As a second background art example there is the semiconductor memory device disclosed in Japanese Unexamined Patent Application, First Publication No. Hei-6-36557. This semiconductor memory device is also provided with an internal timer for conducting refresh operations, and at the point where a predetermined refresh time has elapsed, a refresh start request is generated, and following compl
Inaba Hideo
Kusakari Takashi
Choate Hall & Stewart
Lam David
NEC Electronics Corporation
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