Semiconductor storage

Details Semiconductor storage Semiconductor storage

2006-04-04

2006-04-04

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S100000, C711S117000, C711S123000, C711S136000

Reexamination Certificate

active

07024524

ABSTRACT:
It is an object to obtain a semiconductor storage having a 1—chip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1-port memory cell array (11) provided with a word line (WL1) for a first port in common and a 2-port memory cell array (12) are provided together over one chip, thereby constituting a semiconductor storage. By selectively bringing any of a plurality of the word lines (WL1) for the first port into an active state by a row decoder (16), it is possible to simultaneously access respective memory cells of the 1-port memory cell array (11) and the 2-port memory cell array (12). By selectively bringing any of a plurality of word lines (WL2) for a second port into an active state by a row decoder (18), it is possible to singly access the 2-port memory cell array (12).

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