Semiconductor SRAM with alternatively arranged P-well and...

Details Semiconductor SRAM with alternatively arranged P-well and... Semiconductor SRAM with alternatively arranged P-well and...

2011-08-02

2011-08-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S063000, C365S072000, C365S188000, C365S189140, C365S189050, C365S189080, C365S190000, C365S202000, C365S214000, C365S230030

Reexamination Certificate

active

07990760

ABSTRACT:
A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bit line direction. The cell array includes first P-well regions and first N-well regions shaped in stripes extending in the bit line direction and arranged alternately in the word line direction. The SRAM cell is formed point-symmetrically in the first P-well region and the first N-well regions located on both sides thereof. The peripheral circuit includes second P-well regions and second N-well regions extending in the bit line direction and arranged alternately in the word line direction.

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