Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2002-10-03
2004-06-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257SE27098
Reexamination Certificate
active
06750555
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to memory cell layout of CMOS-type SRAM (Complementary Metal Oxide Semiconductor Static Random Access Memory) among semiconductor memory devices.
The SRAM memory cell that comprises six transistors and is made by a typical semiconductor CMOS process is widely used for system LSIs and so on.
The prior art layout pattern of the CMOS-type SRAM memory cell will be described below with reference to FIG.
8
.
The prior art SRAM memory cell comprises nMOS drive transistors TN
1
and TN
2
, nMOS access transistors TN
3
and TN
4
, pMOS load transistors TP
1
and TP
2
, polysilicon wires PL
1
, PL
2
, PL
3
and PL
4
, wiring layers AL
1
and AL
2
, and contacts CN
1
, CN
2
, CL
1
and CL
2
.
The nMOS drive transistor TN
1
and the nMOS access transistor TN
3
are formed on an n-type diffusion region DN
1
and the nMOS drive transistor TN
2
and the nMOS access transistor TN
4
are formed on an n-type diffusion region DN
2
. The pMOS load transistor TP
1
is formed on a p-type diffusion region DP
1
and the pMOS load transistor TP
2
is formed on a p-type diffusion region DP
2
.
Gates of the nMOS drive transistor TN
1
and the pMOS load transistor TP
1
are connected to each other with the polysilicon wire PL
1
and drains of them are connected to each other with the wiring layer AL
1
via contact, thereby forming a first inverter (CMOS structure). Gates of the nMOS drive transistor TN
2
and the pMOS load transistor TP
2
are connected to each other with the polysilicon wire PL
2
and drains of them are connected to each other with the wiring layer AL
2
via contact, thereby forming a second inverter (CMOS structure). The wiring layer AL
1
as an output node of the first inverter is connected to PL
2
as an input node of the second inverter, and the wiring layer AL
2
as an output node of the second inverter is connected to PL
1
as an input node of the first inverter. Thereby a latch circuit for holding data is formed.
A drain of the nMOS access transistor TN
3
is connected to the wiring layer AL
1
as the output node of the first inverter and source thereof is connected to a bit line (not shown) extending longitudinally via the contact CN
1
. A drain of the nMOS access transistor TN
4
is connected to the wiring layer AL
2
as the output node of the second inverter and source thereof is connected to another bit line (not shown) extending longitudinally via the contact CN
2
. Gates of TN
3
and TN
4
are connected to a word line (not shown) extending transversally via the contacts CL
1
and CL
2
, respectively.
With such memory cell layout, long lateral distance allows a wide interval between two bit lines so that coupling capacitance between bit lines, which may cause a problem in micro process, can be reduced. Therefore, such memory cell layout is advantageous to speeding-up.
Next, relationship between capability ratio of drive transistors and access transistors and stability of data holding in the SRAM memory cell will be explained with reference to
FIGS. 9
,
10
and
11
.
FIG. 9
shows a memory cell circuit diagram for evaluating stability of data holding. This circuit assumes the situation that the access transistors TN
3
and TN
4
turns on when the word line is in VDD level for a reading operation, and the bit line is raised to precharge level.
FIG. 10
shows input/output characteristics of two inverter circuits (INV
1
, INV
2
) in the latch circuit.
Ain-Aout and Bin-Bout represent characteristics of INV
1
and INV
2
, respectively and it is plotted so as to be Ain=Bout and Bin=Aout. Cross points P
1
and P
2
in this drawing are stable points and each point corresponds to memory data
0
or
1
. In the plot, as area surrounded by two curved lines becomes larger, stability of data holding at P
1
and P
2
improves. Here, when driving capability of the access transistors TN
3
and TN
4
becomes greater than that of nMOS transistors (drive transistors) TN
1
and TN
2
in the inverter circuits, input/output characteristics of the inverter circuits change as shown in FIG.
11
. The reason is that the access transistors transmit VDD level of the bit line to the latch nodes more easily, so that area surrounded by two curved lines becomes smaller. When noise voltage is applied into the memory cell having such characteristics, cross points are reduced to be only P
2
′ and therefore the memory cell can hold only either data. That is, in the case where data other than P
2
′ (i.e. P
1
′) is held, the data is destroyed. Thus, maintaining a constant ratio of access transistors to drive transistors in driving capability is important for holding memory cell data stably. Generally, driving capability of access transistors is set to be 50 to 70% of that of drive transistors.
In the prior art SRAM memory cell, channel width of drive transistors is set to be larger than that of access transistors, thereby generating a difference between them in driving capability.
In the prior art SRAM memory cell in which channel width of the drive transistors is set to be larger than that of the access transistors, thereby generating a difference between them in driving capability, the diffusion regions necessarily include some bent parts and end parts. For example, in
FIG. 8
, the bent parts that produce round-offs as shown by dashed lines DL
3
and DL
4
are generated by difference between the nMOS drive transistors TN
1
and TN
2
and the corresponding nMOS access transistors TN
3
and TN
4
in channel width.
With such layout, at the bent parts of the diffusion regions, finish pattern is rounded off as shown by dashed lines DL
1
, DL
2
, DL
3
and DL
4
in the figure. As a result, a problem arises that transistor width of the nMOS transistors TN
1
, TN
2
, TN
3
and TN
4
becomes larger than required. Moreover, at the end parts of the diffusion regions, finish pattern is retreated as shown by dashed-lines DL
5
and DL
6
. As a result, there arises a problem of reduction in overlap margin of the p-type diffusion region with respect to the contact as well as variation in channel width of the pMOS transistors TP
1
and TP
2
.
Furthermore, system mounted on a semiconductor chip has increasingly become large scale. In connection with this, there is a tendency that the block of SRAM with a large scale in bit capacity is mounted on the chip. In order to meet these requests on the system side, it is desired to further reduce the size of SRAM memory cell. Although it is effective to use a MOS transistor with smaller channel width for the purpose of reducing cell size, such small-sized pattern is prone to undergo great variations in characteristics due to processing fluctuations. Therefore, reduction in cell size makes stable design by sufficient operational margin difficult. On the other hand, with recent micro process, it is more difficult to obtain desirable processed form and round-off or retreat of pattern tend to take place. Moreover, there often causes the phenomenon that even the same pattern form changes in finished form due to peripheral pattern form.
To suppress such changes of processed form, it has already been implemented to correct mask pattern in consideration of bend up and bend down of layout pattern concerned and in consideration of the peripheral layout pattern in recent micro process. Such process, however, is sensitive to apparatus used in semiconductor diffusion process and processing conditions. Further, correction value must be modified each time processing conditions in diffusion process are changed, adding a burdensome operation.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-mentioned problems. With the memory cell layout of the semiconductor memory device according to the present invention, it is possible to lay out diffusion regions in linear shapes without any bent part by generating a difference between access transistors and drive transistors in driving capability without changing their channel width. As a result, processed form of diffusion areas of the SRAM memory
Satomi Katsuji
Yamauchi Hiroyuki
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