Measuring and testing – Speed – velocity – or acceleration – Structural installation or mounting means
Reexamination Certificate
2001-09-21
2002-12-17
Moller, Richard A. (Department: 2856)
Measuring and testing
Speed, velocity, or acceleration
Structural installation or mounting means
C073S514310
Reexamination Certificate
active
06494092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor sensor chip used in a wide range of applications such as automobile, aircraft, medical service, measurement, and calibration, and to a production method for manufacturing the sensor chip. It also relates to a semiconductor sensor comprising the semiconductor sensor chip, and to a package for assembling the semiconductor sensor.
2. Description of the Related Art
An example of a conventional acceleration sensor chip disclosed in Japanese Patent No. 2551625 is shown in FIG.
1
A and FIG.
1
B.
FIG. 1A
is a perspective diagram, and
FIG. 1B
is a sectional diagram taken along line IB—IB of FIG.
1
A. In this semiconductor acceleration sensor chip, a silicon single crystal is etched to form a support frame
1
, weight parts
2
a
and
2
b
, a beam part
3
a
for connecting the weight part
2
a
and the weight part
2
b
, and beam parts
3
b
and
3
c
for connecting the weight part
2
a
, the weight part
2
b
and the support frame with each other. Gauge resistors
4
a
,
4
b
,
4
c
, and
4
d
are provided on the beam parts
3
a
,
3
b
, and
3
c
, and a Wheatstone bridge is formed of these gauge resistors. When an acceleration is exerted in a direction shown by the arrow in
FIG. 1B
, resistances of the gauge resistors are changed. The acceleration sensor chip measures the acceleration utilizing changes of the resistances.
In general, in the semiconductor acceleration sensor chip of this kind, a silicon substrate is deeply etched from the backside to form thick-walled weight parts of about 300 &mgr;m to 400 &mgr;m and thin-walled beam parts of about 10 &mgr;m to 50 &mgr;m. As the silicon substrate, a 4 inch wafer is often used. The reason for this is as follows:
Because the substrate is required to be deeply etched to form a thin beam part, a small wafer thickness is advantageous in terms of productivity due to the limitation of processing time. A wafer size which can be handled in the process with a thickness of about 300 &mgr;m to 400 &mgr;m, corresponding to the thickness of the beam part, is about 4 inches, and a larger wafer of 5 or 6 inches is substantially difficult to handle. Further, as shown in
FIG. 1B
, a wafer before dicing is formed with a number of thin-walled, low resonance frequency beam parts and is low in rigidity. A shock applied during dicing tends to generate a resonance phenomenon of the sensor part or the wafer itself, and there is a danger of an excessive displacement or stress applied to the beam parts. Consequently, the wafer size is limited because of this handling.
In the case of the above-described semiconductor acceleration sensor chip, greater part of the cost is determined by chip size and wafer size. When acceleration sensor chips are produced with the same technical level, if the wafer size is large, a large number of chips can be processed in a single batch process, and the unit price of the chip is naturally reduced. However, in the above-described prior art, usable wafer size is limited, and cost reduction can only be achieved by reduction of the chip size. However, the chip size reduction is limited as it may reduce production yield. Further, in the future, with the trend to larger diameter semiconductor wafers, a decrease in supply of 4-inch wafers is anticipated. If such an acceleration sensor chip is achieved with larger-diameter wafers of 5 inches, 6 inches or the like, a beam part of 10 &mgr;m to 30 &mgr;m in thickness must be formed from a silicon substrate of about 600 &mgr;m to 700 &mgr;m in thickness, which not only increases the etching time but also leads to a reduced production yield.
Another example of a prior art acceleration sensor chip is one which is disclosed in Japanese Laid-Open Patent Application No. 8-248058.
The second prior art example will be described with reference to
FIGS. 2A and 2B
.
FIG. 2A
is a perspective diagram of the acceleration sensor chip.
FIG. 2B
is a schematic diagram showing the structure of a comb electrode unit as part of the acceleration sensor chip.
This acceleration sensor chip has a three-layered structure comprising a first layer (support plate)
10
, a second layer
11
as an insulation layer on the first layer, and a third layer
12
coated thereon. For example, it comprises a SOI (silicon-on-insulator) or epitaxial polysilicon wafer (polysilicon as a third layer grown on a single crystal silicon substrate through an insulation layer).
The third layer
12
is provided with a displaceable first support body
13
separated from the first layer
10
and a non-displaceable second support body
16
which is connected with the first layer
10
. The first support body
13
has a mass body
15
disposed at the center and a plurality of first plates
14
extending in a direction perpendicular to the mass body
15
. The second support body
16
has two mounting parts
18
straightly disposed at both ends and a plurality of second plates
17
extending in a direction perpendicular to the mounting parts
18
. The second layers
11
disposed at lower parts of the plurality of first plates
14
and the mass body
15
are removed by etching so that the first support body
13
is displaceable in parallel with respect to the surface of the first layer
10
.
Further, the plurality of first plates
14
and the plurality of second plates
17
respectively form comb electrodes, which, when the displaceable mass body displaces in a direction perpendicular to the first plate
14
, measure an acceleration by utilizing a change in capacitance between the first plate
14
and the second plate
17
. Still further, a conductor
19
for conducting these comb electrodes to an external circuit is electrically insulated from the first layer
10
by the second layer (insulation layer)
11
, and further electrically insulated from the third layer
12
by a cutout
20
.
In the capacitive type acceleration sensor chip using comb electrodes of this type, in order to increase the change in capacitance to affect an increase in sensitivity, it is necessary to form a structure with a decreased rigidity of a movable electrode (first plate
14
). There are two factors that cause variations in sensitivity when such a sensor is constructed. A first factor is a variation in rigidity of the movable electrode (first plate
14
) that is dependent on the production precision, and where the sensitivity is small when the rigidity is high. A second factor is the variation of gap between the movable electrode (first plate
14
) and a fixed electrode (second plate
17
), where the sensitivity decreases as the gap increases.
With respect to the first sensitivity variation factor, in general, production methods such as wet etching, RIE (Reactive Ion Etching), plasma etching and the like are used in process for producing the gap between the movable electrode and the fixed electrode and in the process of producing the support part of the movable electrode. With these production methods, since etching speed in a depth direction varies depending on the processing width, a variation occurs in the processing shape depending on the width of etching pattern. To prevent this, it is necessary to make a complex mask design in consideration of the etching speed which varies for every pattern width, resulting in a complicated process.
The second sensitivity variation factor will now be described in detail. In a sensor chip using a wafer in which polysilicon is formed as a third layer through an insulation layer on a single crystal silicon substrate or a SOI wafer, the second layer comprising an insulation layer, such as SiO
2
, between the first layer and the third layer and a passivation film for protecting circuits on an upper surface of the third layer are formed. As a result, there is a loss of balance in the internal stress between a surface on the side where the second and third layers are disposed on the first layer which controls the rigidity of wafer, and the opposite back surface, resulting in a warped wafer. Therefore, there is a problem in
Nishikawa Mutsuo
Sasaki Mitsuo
Ueyanagi Katsumichi
Frank Robert J.
Fuji Electric & Co., Ltd.
Haddaway Keith J.
Moller Richard A.
Venable
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