Semiconductor ROM wafer test structure, and IC card

Details Semiconductor ROM wafer test structure, and IC card Semiconductor ROM wafer test structure, and IC card

1998-03-13

1999-11-09

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257922, 365195, 324765, G01R 3126

Patent

active

059819715

ABSTRACT:
In a semiconductor wafer (1), an internal circuit such as a ROM formed at a product region or a chip (2) can be tested via a test pad (5) formed on a scribe line (3). Here, since the test pad (5) is formed on the scribe line (3), after the semiconductor wafer has been once cut off and separated away from each other as chips along the scribe lines (3), respectively, since the test pads (5) are all broken off, ROM test will not be executed again. In other words, since the test conditions of the product test of the separated chip (2) cannot be decoded or deciphered by another person, it is possible to provide a semiconductor device of high secrecy, which can be preferably used as an IC card.

REFERENCES:
patent: 4243937 (1981-01-01), Multani et al.
patent: 4446475 (1984-05-01), Gerekci et al.
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5739546 (1998-04-01), Saitou et al.
D. E. Shultis, "Semiconductor Wafer Testing," IBM Technical Disclosure Bulletin, vol. 13, No. 7, Dec. 1970, p. 1793.

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