Semiconductor ROM

Details Semiconductor ROM Semiconductor ROM

1983-07-01

1986-05-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 700

Patent

active

045920249

ABSTRACT:
The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.

REFERENCES:
patent: 3585378 (1971-05-01), Bouricius
patent: 4047163 (1977-09-01), Choate et al.
patent: 4055754 (1977-10-01), Chesley
patent: 4489402 (1984-12-01), Saitoh et al.

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