Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...
Reexamination Certificate
2000-03-20
2001-10-23
Chaudhari, Chandra (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With electric field controlling semiconductor layer having a...
C257S330000, C257S401000, C438S268000, C438S525000
Reexamination Certificate
active
06307246
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and methods of manufacturing the same and in particular to a power semiconductor device used in conjunction with various-types of power supply devices which has low switching loss with low ON resistance and a method of manufacturing the same.
BACKGROUND ART
In Japanese Patent Application No.
9-26997
filed to the Japanese Patent Office on Feb. 10, 1997, the Applicant has proposed a high withstand voltage, vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of the structure shown in FIG.
38
.
Referring to
FIG. 38
, a semiconductor substrate has a first main surface with a plurality of trenches
105
a
repeatedly provided. In a region between trenches
105
a
, p- and n-type diffusion regions
102
and
103
are provided, the former provided on a sidewall surface of one trench
105
a
and the latter provided on a sidewall surface of the other trench
105
a
. P- and n-diffusion regions
102
and
103
provide a p-n junction in the direction of the depth of trench
105
a
(in the figure, vertically).
A p-type well (also referred to as a p-type base region)
107
is provided at p- and n-type diffusion regions
102
and
103
closer to the first main surface. An n
+
source diffusion region
108
is provided in p-type well
107
on a sidewall surface of the other trench
105
a
. A gate electrode layer
110
along a sidewall surface of the other trench
105
a
is provided opposite to p-type well
107
sandwiched between n
+
source diffusion region
108
and n-type diffusion region
103
, with a gate insulation layer
109
posed therebetween.
Trench
105
a
is filled with a filler layer
105
of lightly doped silicon (including monocrystalline-, polycrystalline-, amorphous- and microcrystalline-types of silicon) or an insulator such as silicon oxide film. If filler layer
105
is lightly doped silicon, a p
+
diffusion region
111
in contact with p-type well
107
is provided at filler layer
105
closer to the first main surface.
An n
+
drain region
101
is provided at a second main surface side of a repetition of p- and n-type diffusion regions
102
and
103
and trench
105
a
(referred to as a “p-n repetition structure” hereinafter).
On the first main surface, a source electrode layer
112
is formed, electrically connected to p-type well
107
, n
+
source diffusion region
108
and p
+
diffusion region
111
. On the second main surface, a drain electrode layer
113
is formed, electrically connected to n
+
drain region
101
.
In this structure, with the device in the ON state, an n-type channel is initially induced at a surface of p-type well
107
opposite to gate electrode layer
110
. Then, an electron current flows from n
+
drain region
101
through n-type diffusion region
103
, the n-type channel to n
+
source diffusion region
108
to achieve the ON state.
In the OFF state, for a drain voltage as low as approximately 10 V, a space-charge region along a junction of an n-type region and a p-type region extends therefrom. It should be noted that the n-type region is formed of n
+
drain region
101
and n-type diffusion region
103
that are connected to a drain and that the p-type region is formed of p-type well
107
and p-type diffusion region
102
that are connected to a source. As a drain voltage is increased, n- and p-type diffusion regions
103
and
102
are fully depleted, since regions
102
and
103
both have a reduced thickness.
If a higher drain voltage is applied, the space-charge region expands only towards p-type well
107
and n
+
drain region
101
.
Because of the p-n repetition structure, the RESURF effect can be provided in n-type diffusion region
103
to provide the present MOSFET with higher withstand voltage and lower resistance characteristics than other power MOSFETs. Thus in this structure, it is important that n- and p-type diffusion regions
103
and
102
are provided continuously with a predetermined concentration in the direction of the depth of the trenches (in the figure, vertically).
Description will now be made of a method of fabricating the p-n repetition structure of the present semiconductor device.
FIGS. 39-43
are schematic cross sections illustrating the steps of the method of manufacturing the above semiconductor device. Referring first to
FIG. 39
, on a heavily doped n-type substrate region
101
serving as an n
+
drain region is provided an n- epitaxial growth layer
106
less heavily doped than heavily doped n-type substrate region
101
. A conventional dopant diffusion technique is employed to provide a p-type region
107
serving as a p-type base region on a surface of n- epitaxial growth layer
106
. On p-type region
107
, a thermal oxide film
12
, a chemical vapor deposition (CVD) silicon nitride film
13
and a CVD silicon oxide film
14
forming a 3-layered structure which serves as a mask used in anisotropically etching the underlying layers.
Referring to
FIG. 40
, the anisotropical etch forms a plurality of trenches
105
a
extending from a first main surface to reach heavily doped n-type substrate region
101
.
Referring to
FIG. 41
, oblique ion implantation is employed to implant boron (B) into one sidewall surface of trench
105
a
to provide boron-implanted region
102
a.
Referring to
FIG. 42
, oblique ion implantation with an inclination opposite to that applied in the above boron implantation is employed to implant phosphorus (P) into the other sidewall surface of trench
105
a
to provide a phosphorus-implanted region
103
a.
Referring to
FIG. 43
, a CVD silicon oxide film
105
serving as an insulation film fills trench
105
a
and also covers 3-layered structure
12
,
13
,
14
. Thermal treatment is then applied to diffuse the p- and n-types of dopants introduced through ion implantation. Thus n- and p-type diffusion regions
102
and
103
are provided in a region between trenches
105
a
to provide the p-n repetition structure.
In the
FIG. 38
semiconductor device, however, the depth of p- and n-type diffusion regions
102
and
103
from the first main surface is substantially equal to that of trench
105
a
from the first main surface. This disadvantageously provides a low OFF-state withstand voltage and a high ON-state resistance. This disadvantage will now be detailed below.
In the above manufacturing method, ions are obliquely implanted, as shown in
FIGS. 41 and 42
. In this oblique ion implantation, a certain percentage of the ions are reflected at a sidewall of trench
105
a
, as shown in
FIG. 44
(as indicated by the dotted arrows). As such, reflected ions
120
are implanted into a sidewall opposite to a targeted sidewall, i.e., a bottom of trench
105
a.
In effect, trench
105
a
has its bottom rounded (with a definite curvature), as shown in FIG.
45
. As such, ions incident directly on the bottom (indicated by the solid arrow) and those reflected at a sidewall and thus incident on the bottom (indicated by the dotted arrow) are reflected at the bottom of trench
105
a
and thus intensively implanted into a sidewall which is opposite to a targeted sidewall and is also a bottom of trench
105
a.
As such, if p- and n-type diffusion regions
102
and
103
are substantially as deep as trench
105
a
, a portion with a significantly varied doping concentration (a portion with a locally varied concentration) is developed at a bottom internal to p-type diffusion region
102
and that internal to n-type diffusion region
103
. Furthermore, a region with its conductivity inverted from the p- to n-type or vice versa can also be developed at bottoms internal to p- and n-type diffusion regions
102
and
103
. As a result, p- and n-type diffusion regions
102
and
103
fail to have a uniform or continuous profile of doping concentration in a direction perpendicular to the first main surface. As such, when p- and n-type diffusion regions
102
and
103
are depleted in the OFF state an uneven electric field is created resulting in a
Minato Tadaharu
Nitta Tetsuya
Uenisi Akio
Chaudhari Chandra
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pert Evan
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