Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-08-28
2003-03-25
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S203000, C257S620000, C257S208000, C257S210000, C257S202000, C257S784000, C257S786000
Reexamination Certificate
active
06538264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor reliability test chip. More specifically, the present invention relates to a semiconductor reliability test chip including a plurality of test functions.
2. State of the Prior Art
Typically, the reliability of semiconductor products has been tested by operating the semiconductor products in a variety of life accelerating environments over periods of time until the components fail. Subsequently, the semiconductor components are inspected and tested electrically in an attempt to determine the cause of failure. Since there are many reasons for the failure of semiconductor components, the analysis of failed components can be lengthy and difficult. Attempts have been made to design semiconductor test chips or dies to assess a specific type of failure of the semiconductor component. An article by J. S. Sweet, entitled “The Use of Special Purpose Assembly Test Chips for Evaluating Reliability In Packaged Devices”, published by Sandia National Laboratory, pages 15-19, describes some of these types of chips. The article describes a series of individual special purpose assembly test chips to aid in assessing the reliability of packaged integrated circuits. The special purpose assembly test chips contain special purpose circuits or sensors which enhance the detection of failures or detect moisture, detect mobile ions, or other contaminants which can lead to failure of the semiconductor component.
In U.S. Pat. No. 5,414,351, a method is described for testing the reliability of terminals in a semiconductor package by placing a test chip in the package wherein the test chip has an insulating substrate, a passivating layer over the metal layer provided with a plurality of openings, a plurality of Gold (Au) terminals in the openings bonded to the metal layer and a master ground terminal bonded to the metal layer. Input/Output (I/O) terminals are provided in the package structure for each of the Au terminals, master terminals are connected to the I/O terminals with wire, and the test chip is sealed in a package. The resistance of each terminal is monitored to determine any change of electrical resistance, which is an indication of terminal deterioration.
U.S. Pat. No. 5,329,228 discloses a semiconductor test chip for use in semiconductor fabrication fault analysis comprising an n×m array of transmission gate cells arranged such that, within a given row, respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row. The sources and drains of each row are independent and within a column of strips of conductive material of a second type forming common gate electrodes such that each column of transistors can be turned on independently. The results of the semiconductor test chip are useful for characterizing process yields and reliability as well as useful for high level yield modeling.
U.S. Pat. No. 5,326,428 describes a method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry to test the operability thereof. The patent further describes a test probe suitable for use with the substrate.
U.S. Pat. No. 5,214,657 describes circuitry to enable dicing of a wafer of semiconductor chips. The circuitry is included in the street area of the chips forming the wafer.
U.S. Pat. No. 5,059,899 discloses a method for producing individual semiconductor chips from wafers, wherein the test pads for the testing of individual dies or chips are formed in the scribe or street area of the chip.
U.S. Pat. No. 4,420,722 discloses a technique for testing for heavy metal contamination in semiconductor processing furnaces through the use of a specially designed semiconductor chip having a plurality of PN-junctions, at least one of which is completely isolated from the sides of the chip. The specially designed semiconductor chip is manufactured to exhibit a high reverse recovery time which is measured and compared to determine if it has decreased over time.
U.S. Pat. No. 4,360,142 discloses the use of dummy semiconductor chips in developing improved solder bonds.
U.S. Pat. Nos. 3,746,973, 3,803,483, and 5,341,685 disclose the use of test chips to test semiconductor chips or apparatus for use in the testing of lead tab bonds and semiconductor chips.
In contrast to the prior art, a more comprehensive type test chip is desirable to facilitate evaluation of the effects of bond pad spacing and size on manufacturing and bond integrity. Also, a test chip is needed to study the bonding effects of the use of thinner metal layers forming the bond pads and the effects of the use of films beneath the metal of bond pads as stress buffers during wire bonding. Further, a test chip is needed to study the thermal effects of the chip in a variety of packaging arrangements. Additionally, a test chip is needed to study the effects of ion mobility in conventional thick and thin film type gate structures including having a temperature measurement capability therewith.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip of the present invention include bond pad pitch and size effects on chip design, wire bond placement accuracy relating to placement of the wire bond on the bond pad, evaluation of the effect of bond pad damage on the area of the chip below the bond pad during bonding of the wire on the bond pad (cratering), street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities, and chip on board in flip chip application test capabilities. A substantially square die is used in the present invention to provide the maximum assembly flexibility with lead frames.
REFERENCES:
patent: 3746973 (1973-07-01), McMahon, Jr.
patent: 3803483 (1974-04-01), McMahon, Jr.
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4360142 (1982-11-01), Carpenter et al.
patent: 4420722 (1983-12-01), Todd
patent: 4599576 (1986-07-01), Yoshida et al.
patent: 4992845 (1991-02-01), Arakawa et al.
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5068603 (1991-11-01), Mahoney
patent: 5157476 (1992-10-01), Yoshida
patent: 5214657 (1993-05-01), Farnworth et al.
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5329228 (1994-07-01), Comeau
patent: 5341685 (1994-08-01), Malone
patent: 5347150 (1994-09-01), Sakai et al.
patent: 5351001 (1994-09-01), Kornrumpf et al.
patent: 5365091 (1994-11-01), Yamagishi
patent: 5399914 (1995-03-01), Kozono
patent: 5414351 (1995-05-01), Hsu et al.
patent: 5448088 (1995-09-01), Nagai et al.
patent: 5455460 (1995-10-01), Hongo et al.
patent: 5466956 (1995-11-01), Aeba
patent: 5481125 (1996-01-01), Harris
patent: 5489538 (1996-02-01), Rostoker et al.
patent: 5528083 (1996-06-01), Malladi et al.
patent: 5723906 (1998-03-01), Rush
patent: 5757082 (1998-05-01), Shibata
patent: 5801450 (1998-09-01), Barrow
patent: 5923047 (1999-07-01), Chia et al.
patent: 5939790 (1999-08-01), Gregoire et al.
patent: 1-100936 (1989-04-01), None
patent: 3-82129 (1991-04-01), None
patent: 4-7865 (1992-01-01), None
patent: 5-29546 (1993-02-01), None
patent: 5-343525 (1993-12-01), None
patent: 6-77299 (1994-03-01), None
Shirley et al.; “A Technique for Electrical Measurement of Ball Bond Location”; Proceedings of the 38th Electronics Components Conference of the IEEE; 1988; pp. 564-569.
Sweet; “The Use of Special Purpose Assembly Test Chips for Evaluating Reliability in Packaged Devices”; WLR Workshop; Jul. 27, 1992; pp. 1-3.
Corbett Tim J.
Gonzalez Fernando
Scholer Raymond P.
LandOfFree
Semiconductor reliability test chip does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor reliability test chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor reliability test chip will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3061865