Semiconductor redundant memory provided in common

Details Semiconductor redundant memory provided in common Semiconductor redundant memory provided in common

2002-08-13

2003-03-25

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

C711S105000, C711S220000, C711S005000, C714S711000, C365S200000

Reexamination Certificate

active

06539452

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor memory, and more particularly to a new configuration for redundant circuitry utilized in the burst mode in a 2-bit pre-fetch circuit or a multi-bit pre-fetch circuit of a synchronized dynamic random access memory (SDRAM).
2. Description of the Related Art
A synchronized DRAM (hereafter referred to simply as SDRAM) is a DRAM that performs internal operations in synch with a system-supplied clock, and is capable of faster operation than an ordinary DRAM. This SDRAM is also supplied with system-supplied command signals, which specify operating modes. By internally decoding these applied command signals, the SDRAM determines the system-requested operating mode, and, for example, outputs read data in accordance with a specified operating mode.
One of the above-mentioned operating modes is a burst mode. Increasing clock speeds have made it impossible for internal memory operations to be performed within a single clock cycle. This burst mode allows the simultaneous reading and writing of a plurality of addresses, and writes or outputs the memory data of sequential addresses that have an externally-supplied address as their starting address. Accordingly, the number of sequentially outputted bits are specified as 2-bit, 4-bit or 8-bit.
With such a burst mode, an SDRAM internally generates consecutive addresses based on an external address, and outputs memory data by decoding these addresses. With a 2-bit burst mode, a single internal address is generated. With a 4-bit burst mode, one internal address is generated, and during the next clock cycle, two internal addresses are generated. And with an 8-bit burst mode, one internal address is generated, and during the next three clock cycles, two internal addresses are generated per cycle.
Under these circumstances, the internal memory cell array of an SDRAM is divided into an odd address memory cell array and an even address memory cell array, and in the burst mode, an SDRAM supplies an externally-supplied or internally-generated address, whose least significant bit is removed, to the column decoders of the odd address memory cell array and the even address memory cell array. The use of such an architecture enables the sequential output of 2-bit memory data at all times. This architecture is called a 2-bit pre-fetch circuit. Similarly, a 4-bit pre-fetch circuit, which enables the simultaneous reading and writing of 4-bit memory data, is also possible. In this case, addresses whose least significant two bits are removed are supplied to the respective column decoders of four memory cell arrays.
FIG. 1
depicts an example of a 2-bit pre-fetch circuit in a conventional SDRAM. In this example, the memory cell array is divided into an odd address memory cell array
10
and an even address memory cell array
20
. And for each memory cell array
10
,
20
, an address predecoder
11
,
21
and address main decoder
12
,
22
are provided. In addition, the output from each memory cell array
10
,
20
is amplified by a data bus amp
13
,
23
.
SDRAM operates in synch with a system-supplied clock CLK. Therefore, according to the timing of a clock
31
outputted from a clock buffer
30
, which captures the clock CLK, a command signal
2
(Comm) is latched to a command latch & decoder
32
, and an address signal
3
(Add) (in this example, eight bits from a
0
to a
7
) is latched to an address buffer
33
. And then, an address signal a
3
-a
7
from the address buffer
33
is latched to an address latch
38
based on the timing of an address latch clock
35
generated by the command latch & decoder
32
. An address signal a
1
, a
2
is also latched to an address latch and counter
39
based on the same clock
35
.
An address signal a
3
-a
7
is supplied as is to odd and even address predecoders
11
,
21
. Meanwhile, an address a
1
, a
2
is supplied as-is to the odd address predecoder
11
. An address a
1
, a
2
is also supplied to the even address predecoder in accordance with the value of the least significant address a
0
, that is, according to whether it is odd or even, either as-is as a latched address
44
or as a new shifted address
48
, in which the address is incremented by 1 by an address arithmetic circuit
46
.
Thus, when the external address is even, even memory data
24
amplified by an even data bus amp
23
is latched to an output data latch
16
based on clock
56
timing, and then odd memory data
14
amplified by an odd data bus amp
13
is latched to an output data latch
26
based on clock
57
timing, and even and odd data are sequentially outputted in that order through output terminal DOUT.
Further, when the external address is odd, odd memory data
14
is latched to the output data latch
16
, and even memory data is latched to the output data latch
26
, based on timing supplied by clocks
56
,
57
, respectively, and odd and even data are sequentially outputted in that order.
In line with increasing memory capacity, a redundant cell array is being added to a memory cell array to prevent a drop in memory yield. In line with adding such a redundant cell array, it is necessary to provide a redundant address read-only memory (ROM), which stores the address of a defective cell substituted for by a redundant cell array, and an EOR circuit, or a redundant address comparator, which determines whether or not this redundant address matches the address currently being accessed.
However, when a redundant cell array architecture is applied to memory in the above-described 2-bit pre-fetch circuit architecture, because there are an internal odd address cell array
10
and even address cell array
20
, it is necessary to provide a redundant cell array, and both a redundant column address ROM and redundant address comparator for each cell array. Firstly, since this involves providing duplicate redundant column address ROM and redundant address comparators, the size of the circuit architecture increases. And secondly, when a redundant cell array is provided for both the odd and even cell arrays, when each has a redundant column address ROM, these redundant column address ROM cannot be used efficiently. That is, judging from the probability of a defective cell occurring, there is less probability of both the odd address cell array and the even address cell array using an entire redundant cell array. Therefore, there is an extremely low probability both redundant column address ROM for both cell arrays will utilize 100% of their capacity for storing redundant addresses. The above-mentioned problem is the same for a 4-bit pre-fetch architecture, and is generally also the same for multi-bit pre-fetch architectures.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a semiconductor memory with an efficient architecture for the redundant circuitry of a redundant cell array for a multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant ROM, which stores a redundant address of a redundant circuit of a redundant cell array for a 2-bit or larger multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for redundant address wiring from a redundant column address ROM to a redundant address comparator.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant address comparator of a redundant circuit of a redundant cell array for a 2-bit or larger multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant address comparator of a redundant circuit.
To achieve the above-stated objects in a memory, in which an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant

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