Semiconductor read/write memory array having high speed serial s

Static information storage and retrieval – Read/write circuit – Data refresh

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3072384, 357 40, 365189, G11C 1140

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active

042814014

ABSTRACT:
A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

REFERENCES:
patent: 3560940 (1971-02-01), Gaensslen
patent: 4127899 (1978-11-01), Dachtera

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