Semiconductor read only memory with paralleled selecting transis

Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge

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Details

365 63, 365 72, 365104, 36523003, 36523006, G11C 700

Patent

active

053413377

ABSTRACT:
A semiconductor ROM includes a plurality of word lines disposed in parallel and has a plurality of units which each includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth, sub-bit lines disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. First ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line. First and second ones of the bank selecting switches are disposed in parallel between the first main bit line and the first sub-bit line, and third and fourth ones of the bank selecting switches are disposed in parallel between the second main bit line and the fourth sub-bit line. A fifth one of the bank selecting switches is disposed between the first main bit line and the third sub-bit line, and a sixth one of the bank selecting switches is disposed between the second main bit line and the second sub-bit line.

REFERENCES:
patent: 4281397 (1981-07-01), Neal et al.
patent: 5023681 (1991-06-01), Ha
patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5117389 (1992-05-01), Yiu
patent: 5202848 (1993-04-01), Nakagawara
patent: 5268861 (1993-12-01), Hotta
patent: 5295092 (1994-03-01), Hotta

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