Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-10
2002-09-10
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S208000, C365S104000
Reexamination Certificate
active
06448617
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a semiconductor read-only memory configuration having a semiconductor substrate and a to multiplicity of memory cells configured in a memory cell array in the semiconductor substrate. Each memory cell includes a plurality of transistors. The memory configuration includes word lines composed of polycrystalline silicon, and includes metal tracks, which run parallel to the word lines and which are isolated from the latter by an intermediate insulator. The word lines are ruptured in their longitudinal direction in each case after a first number of memory cells and can be refreshed via the metal tracks. A reference-ground potential can be applied to the semiconductor substrate via a substrate contact, in each case, after a second number of memory cells.
As is known, there are semiconductor read-only memory configurations with so-called diffusion read-only memories (ROMs) and so-called contact ROMs. In the case of diffusion ROMs, a diffusion is finally introduced in the entire memory cell array through a customized definition, while in the case of contact ROMs, the last step consists in providing the respective contacts in a manner corresponding to the customized definition. The diffusion involves the introduction of source zones and drain zones, while source contacts and drain contacts are created during the provision of the contacts.
In detail, in a memory cell array, the individual memory cells or the MOS field-effect transistors are completed except for the source and the drain diffusion or except for the source and the drain contacts. In accordance with the memory content to be stored in the read-only memory configuration, the individual transistors are then provided with the source and the drain diffusion or with the source and the drain contacts. In this case, a transistor with diffusion (or contacts) signifies a logic “0”, while a transistor without diffusion (or without contacts) is assigned a logic “1”. In other words, if a transistor is present, then this means a logic “0”, while the absence of a transistor through the absence of diffusion or contacts is assigned to a logic “1”.
In the memory cell array of such a semiconductor read-only memory configuration, it is necessary, then, to effect a well contact connection, a so-called rupture of the word line and a metal/polysilicon bridge. In the case of the well contact connection, a so-called substrate contact applies the reference-ground potential Vss to the well zone of the memory cells, while the word line is ruptured, since the polycrystalline silicon forming the word line must be interrupted after specific lengths for capacitance reasons or according to the so-called “ESD (Electrostatic Discharge) rules”. Moreover, it is necessary for the signals impressed on the polycrystalline silicon of the word lines likewise to be refreshed after a specific length. This is done, then, as follows: after a technology-dependent x-fold, for example 100-fold, width of a transistor via which a word line is led, the polycrystalline silicon thereof is interrupted and the word line is refreshed by a metal/polysilicon bridge. For this metal/polysilicon bridge, a metal track made, for example, of aluminum or copper runs above the polycrystalline silicon of the word line, and is isolated from the latter by an intermediate insulator made, for example, of silicon dioxide. In order to refresh a signal that is transferred by the polycrystalline silicon of the word line, a connection is established between the metal track and the polycrystalline silicon.
If it is assumed that, by way of example, eight transistors arranged in two rows form a memory cell, then after a first number of memory cells, for example three memory cells, a substrate contact is provided, while a rupture of the word line or of the refresh thereof is in each case performed after a second number of memory cells, for example, nine memory cells.
The well contact connection with the substrate contacts and also rupture and refresh of the word line thus do not take place in the memory cells of the memory cell array, but rather at regular intervals along the individual word lines. This inevitably necessitates further intermediate cells. In each case, after a first number of memory cells, an intermediate cell is provided for a substrate contact for the well contact connection, while rupture and refresh of the word line are effected, in each case, after a second number of memory cells.
FIG. 3
shows a plan view of a conventional semiconductor read-only memory configuration having memory cell arrays 1 to 3, which each include memory cells having 4×2 transistors. After every three memory cells (in this respect cf. an upper row
4
of these memory cells), an intermediate cell
5
is present with a substrate contact via which reference-ground potential Vss is applied to the well of the memory cell arrays 1 to 3. At an interval of every nine memory cells, there is a rupture and a refresh of the word lines WL is performed at intermediate cells
6
. Here, the polycrystalline silicon of the word lines is interrupted, and in each case, is connected by the overlying intermediate insulator to the metal track that is guided thereon.
Thus, in the case of the existing semiconductor read-only memory configuration, a relatively large amount of space is required for the intermediate cells, as can be seen from the plan view of FIG.
3
.
FIG. 4
shows one of the intermediate cells
5
on an enlarged scale. A metal layer or track
7
is arranged above a word line WL made of polycrystalline silicon, is isolated from the latter by an intermediate insulator, and runs parallel to the polycrystalline silicon of the word line WL. A metalization layer
8
is provided above this metal track
7
, which is likewise isolated from the metal track
7
by an intermediate insulator. This metalization layer
8
feeds reference-ground potential Vss, via a substrate contact
9
, to the well of the memory cell arrays.
FIG. 5
shows an intermediate cell
6
with an interruption or a rupture
10
of the polycrystalline silicon of the word line WL. A plated-through hole
11
is provided between the respective metal track
7
and the polycrystalline silicon of the underlying word line WL, and a substrate contact
12
is provided.
To summarize, then, it must be emphasized that two different intermediate cells are required in existing semiconductor read-only memory configurations. The first intermediate cells serve for well contact connection, while rupture, refresh and well contact connection of the polycrystalline silicon of the word lines are performed in the second intermediate cells. Overall, this requires that the two intermediate cells occur frequently, which necessarily entails a reduction in the number of actual memory cells between the intermediate cells. Ultimately, this means that memory space is lost in the semiconductor read-only memory configuration, which is a critical obstacle to further miniaturization of the configuration.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor read-only memory configuration which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide a semiconductor read-only memory configuration which requires less space through the use of fewer intermediate cells for substrate contacts, rupture and refresh, and thus allows the area that is available for the actual memory cells to be enlarged.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor read-only memory configuration, that includes: a semiconductor substrate; a memory cell array located in the semiconductor substrate; a plurality of memory cells configured in the memory cell array, each one of the plurality of memory cells including a plurality of transistors; word lines made of polycrystalline silicon, the word lines running in a longitudinal direc
Martin Ekkart
Ostermayr Martin
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Ngo Ngan V.
Stemer Werner H.
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