Semiconductor random access memory device having switchable inpu

Details Semiconductor random access memory device having switchable inpu Semiconductor random access memory device having switchable inpu

1986-07-07

1988-08-09

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365230, 365189, G11C 700

Patent

active

047633042

ABSTRACT:
A semiconductor random access memory device having input terminals for receiving multi-bit data and output terminals for transmitting multi-bit data includes a memory cell matrix connected to a number of pairs of data lines and including a number of memory cells. Also included is an address decoder circuit which is responsive to an external address signal for providing address selection signals and a number of data input control circuits for receiving both 1-bit data signal and 1-bit signals of the multi-bit data and for providing as a pair of complementary signals either the 1-bit data signal or the one bit signal of the multi-bit data signal in response to various signals input thereto. A number of data input/output switching circuits and bit data output control circuits and 1-bit data output circuits and bit signal output control circuits are also provided for properly outputting either the 1-bit data or one bit signal of the multi-bit data from the output of the semiconductor random access memory device.

REFERENCES:
patent: 4099253 (1978-07-01), Dooley, Jr.
patent: 4354256 (1982-10-01), Miyasaka
patent: 4675849 (1987-06-01), Kinoshita

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