Semiconductor random access memory cell on silicon-on-insulator

Details Semiconductor random access memory cell on silicon-on-insulator Semiconductor random access memory cell on silicon-on-insulator

1994-04-29

1995-08-29

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257321, 365185, H01L 27115, H01L 29788

Patent

active

054462991

ABSTRACT:
A stacked gate memory cell for a memory cell array is disclosed that is constructed on a SOI substrate and contains a second control gate buried underneath the conducting channel of the cell in addition to a first wordline control gate that is disposed over a floating gate changing the voltage on the second control gate will modulate the potential of the floating channel, which allows a specific cell of the array to be selected and the programmed or erased by FN tunneling through the floating gate and channel without disturbing adjacent cells. While reading the information stored in the floating gate, the second control gate can also be used to prevent disturb. The second control gate is in parallel with the bit line and perpendicular with the first word line control gate. The floating gate and the cell is located at the cross point of the first and second control gates. Therefore, by varying the voltage on the first and second control gates only, the cell can be programmed or erased through FN tunneling.

REFERENCES:
patent: 2310970 (1943-12-01), Okazawa
patent: 4297719 (1981-10-01), Hsu
patent: 4334347 (1982-06-01), Goldsmith et al.
patent: 4999313 (1991-03-01), Arikawa et al.
patent: 5055898 (1991-10-01), Beilstein, Jr. et al.
IBM Technical Disclosure Bulletin, vol. 34, No. 6, Nov. 1991, pp. 238-241 "Vaccum-Sealed Silicon-Rich -Oxide EEPROM Cell".

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