Semiconductor random access memory

Details Semiconductor random access memory Semiconductor random access memory

2000-05-26

2001-04-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S203000

Reexamination Certificate

active

06219272

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor random access memory in which bit lines are pre-charged to access to one of a plurality of memory cells and are discharged in a data outputting operation.
2. Description of Related Art
FIG. 6
is a circuit view showing a configuration of a conventional semiconductor random access memory.
As shown in
FIG. 6
, symbols M
mn
(m=1,2,3, . . . ,M, and n=1,2,3, . . . ,N) denote a plurality of memory cells arranged in a matrix shape (M rows and N columns), and high level data (called “H” data) or low level data (called “L” data) is stored in each of the memory cells M
mn
. Symbols BLn denote a plurality of bit lines arranged in parallel to each other in the columns in one-to-one correspondence. Each of the bit lines BLn is set to a high (“H”) level in a pre-charge operation, and each bit line BLn is maintained to the “H” level or is changed to a low (“L”) level in a reading operation and a writing operation. Symbols BLn′ denote a plurality of bit lines arranged in parallel to each other in the columns in one-to-one correspondence so as to make one pair of bit lines BLn and BLn′ for each column. Each of the bit lines BLn′ is set to the “H” level in the pre-charge operation, and each of the bit lines BLn′ is changed or maintained to the “L” or “H” level opposite to the level of the corresponding bit line BLn in the reading operation and the writing operation. Symbols WLm denote a plurality of word lines arranged in parallel to each other in the rows in one-to-one correspondence and crossing over the bit lines BLn and BLn′. Each of the word lines WLm transmits a row selection signal set to the “H” level in the reading operation and the writing operation. Symbols T
amn
denote a plurality of first n-channel transistors (functioning as first transistors) in which each gate electrode is connected to the corresponding word line WLm. Each of the first n-channel transistors T
amn
connects electrically the bit line BLn with a first side of the memory cell M
mn
to equalize the electric level of the bit line BLn with that of the first side of the memory cell M
mn
in cases where the row selection signal transmitting through the corresponding word line WLm is input to the gate electrode. T
bmn
denotes a plurality of second n-channel transistors (functioning as second transistors) in which each gate electrode is connected to the corresponding word line WLm. Each of the second n-channel transistors T
bmn
connects electrically the bit line BLn′ with a second side of the memory cell M
mn
to equalize the electric level of the bit line BLn′ with that of the second side of the memory cell M
mn
in cases where the row selection signal transmitting through the corresponding word line WLm is input to the gate electrode. A reference numeral
6
denotes a pre-charge control signal line. The pre-charge control signal line
6
transmits a pre-charge control signal indicating a time-period of the pre-charge operation for each cycle.
Symbols PRn denote a plurality of pre-charge circuits. Each of the pre-charge circuits PRn pre-charges the corresponding pair of bit lines BLn and BLn′ during the time-period of the pre-charge operation indicated by the pre-charge control signal transmitting through the pre-charge control signal line
6
to set the electric levels of the bit lines BLn and BLn′ to the “H” level.
A reference numeral
7
denotes an address latch. The address latch
7
receives an address signal, which indicates an address (i,j) of a particular memory cell M
ij
to be accessed, from a central processing unit (not shown) or the like a-nd holds address data indicating a particular row and a particular column as the address (i,j) of the particular memory cell M
ij
. A reference numeral
8
denotes a row decoder. The row decoder
8
decodes the address data of the particular memory cell M
ij
held in the address latch
7
to specify the particular row and to heighten the electric level of a particular word line Wi corresponding to the particular row of the particular memory cell M
ij
to the “H” level in the reading operation. The first n-channel transistor T
aij
and the second n-channel transistor T
bij
corresponding to the particular memory cell M
ij
are turned on, and the electric levels of a particular pair of bit lines BLj and BLj′ are equalized with those of the sides of the particular memory cell M
ij
.
A reference numeral
9
denotes a column selector. The column selector
9
selects the particular pair of bit lines BLj and BLj′ according to the address data held in the address latch
7
. A reference numeral
10
denotes a sense amplifier. The sense amplifier
10
detects a pair of electric levels of the particular pair of bit lines BLj and BLj′ selected in the column selector
9
. A reference numeral
11
denotes an output control circuit. The output control circuit
11
performs an output control for the pair of electric levels of the particular pair of bit lines BLj and BLj′ detected in the sense amplifier
10
. A reference numeral
12
denotes a data bus. The data bus
12
transmits the pair of electric levels, which are output-controlled in the output control circuit
11
and indicate the “H” data or the “L” data stored in the particular memory cell M
ij
, to an external apparatus.
FIG. 7
is a circuit view showing a configuration of each memory cell M
mn
.
Each memory cell M
mn
is a latch circuit which is composed of a pair of inverters directed to different directions in parallel to each other to set electric levels of the first and second sides of the memory cell M
mn
to different levels. In cases where the “H” data (or the “L” data) is stored in the memory cell M
mn
, the first side of the memory cell M
mn
facing on the bit line BLn is set to the “H” level (or “L” level), and the second side of the memory cell M
mn
facing on the bit line BLn′ is set to the “L” level (or “H” level).
In the above configuration, an operation of the conventional SRAM is described with reference to FIG.
8
.
FIG. 8
shows the relationship of electric levels (“H” and “L” levels) of a plurality of signals and lines of the conventional SRAM.
In this operation, the “H” data stored in the memory cell M
11
, the “L” data stored in the memory cell M
21
and the “H” data stored in the memory cell M
12
are, for example, read out in that order.
As shown in
FIG. 8
, the “H” data of the memory cell M
11
is read out in a first cycle, the “L” data of the memory cell M
21
is read out in a second cycle, and the “H” data of the memory cellM
12
is readout inathird cycle. Indetail, a pre-charge operation is performed in the first half of the first cycle by using the pre-charge circuits PRn to set all bit lines BLn and BLn′ to the “H” level. Thereafter, in the second half of the first cycle, address data, which indicates an address (1,1) of the memory cell M
11
and is held in the address latch
7
, is decoded in the row decoder
8
, the word line WL
1
corresponding to the memory cell M
11
is selected according to the decoded data, and the word line WL
1
is set to the “H” level by the row decoder
8
to
15
transmit a row selection signal to the memory cells M
1
n
. Therefore, the gate electrodes of the first n-channel transistor T
a
11
and the second n-channel transistor T
b
11
are set to the “H” level according to the row selection signal, the first n-channel transistor T
a
11
and the second n-channel transistor T
b
11
are turned on, the first side of the memory cell M
11
set to the “H” level is electrically connected with the bit line BL
1
, the second side of the memory cell M
11
set to the “L” level is electrically connected with the bit line BL
1
′, and the bit line BL
1
is maintained to the “H” level because the electric level of the bit line BL
1
is the same as that of the first side of the memory cell M
11
. In contrast, because the electric le

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