Semiconductor random access memory

Communications: electrical – Digital comparator systems

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307238, 307279, G11C 1140

Patent

active

039597814

ABSTRACT:
A random access memory system employing dynamic storage wherein each cell comprises a single active element. The memory employs MOS technology and is disposed on a silicon substrate. A plurality of sense amplifiers are disposed in a column substantially bisecting each row of memory cells in the memory array. A single input/output line communicates with all the cells. Two dummy cells are employed on each row line on opposite sides of the sense amplifiers. The value of the signal provided by the dummy cell is approximately mid-way between a "0" signal and a "1" signal provided by the storage cells. A plurality of timing signals are generated within the memory; accurate timing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3699537 (1972-10-01), Wahlstrom

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