Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-27
2002-04-02
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S362000
Reexamination Certificate
active
06365939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a protection element for preventing plasma damage.
2. Description of the Related Art
When fabricating a MOS (Metal Oxide Semiconductor), various types of plasma processes are performed for a substrate such as deposition of a CVD (Chemical Vapor Deposition) film by a plasma CVD method, formation of contact holes through an interlayer insulator film by plasma etching, patterning of a wire layer by plasma etching and removal of an etching mask by plasma ashing.
During plasma processes, semiconductor wafers on which MOS transistors are formed are exposed to plasma. The plasma consists of charged particles such as ions and electrons, and these charges can move to the semiconductor substrate, and are accumulated on the MOS transistors through the exposed conductors such as wires connected to the MOS transistors. This phenomenon is called antenna effect, and a wire that gives rise to the antenna effect is called an antenna. If the amount of the accumulated charges exceeds a certain value, then the charges escape to the substrate by passing through the gate oxide film of the MOS transistor, and the gate oxide film is damaged.
Usually, damage of the type just described is called plasma damage.
The problem of plasma damage is described in the case of an NMOS transistor shown in
FIG. 1
, which shows a schematic sectional view of an NMOS transistor on the substrate.
The NMOS transistor is formed in a p-well
14
on a p-type substrate
12
. A pair of n
+
diffusion regions (source/drain regions)
16
A and
16
B are formed in the p-well
14
, and a gate electrode
20
is formed on the p-well
14
with a gate oxide film
18
interposed therebetween. Further, an interlayer insulator film
22
covers an entire area of the n
+
diffusion regions (source/drain regions)
16
A and
16
B and the gate electrode
20
.
After the interlayer insulator film
22
is formed, contact holes through the interlayer insulator film
22
are formed by plasma etching. After the contact holes are formed, plasma process steps such as plasma ashing to remove the remaining photo-resist as a mask for contact hole formation, or a step of patterning a metal film deposited on the interlayer insulator film
22
by plasma etching, and so forth are performed.
During plasma processes, a large amount of charges are generated in the plasma. The charges generated in the plasma are accumulated on the gate electrode
20
by the antenna effect of the gate electrode
20
or a conductor connected to the gate electrode
20
. If the accumulated charges in the gate electrode
20
exceed a predetermined amount, then they discharge into the p-type substrate
12
through the gate oxide film
18
. Upon the discharge, the gate oxide film
18
is damaged.
A similar problem occurs also in the case wherein a CVD film is deposited by a plasma CVD method in order to form the interlayer insulator film
22
on the gate electrode
20
.
Therefore, in order to let the charges accumulated on the gate electrode
20
escape to the p-type substrate
12
and thus to prevent the gate oxide film
18
of the NMOS transistor
10
from being damaged by the plasma processes, the NMOS transistor
10
is provided with a protection circuit that includes a protection element for discharging the accumulated charges safely.
Since the charge has a polarity of either positive or negative, the NMOS transistor
10
is provided with two kinds of protection elements that allow positive charges and negative charges to escape to the substrate. Thus the protection element includes a first protection element
24
and a second protection element
28
.
The first protection element
24
is a n
+
/p-well diode composed of the p-well
14
and an n
+
diffusion region
26
formed separately from the n
+
diffusion regions
16
A and
16
B in the p-well
14
.
If the gate electrode
20
is charged with negative charges, then the negative charges escape to the p-type substrate
12
through the n
+
/p-well diode
24
, which provides a low resistance current path because the n
+
/p-well diode
24
is forward biased.
The second protection element
28
is a p
+
-well diode composed of an n-well
30
formed adjacent the p-well
14
and a p
+
diffusion region
32
formed in the n-well
30
.
If the gate electrode
20
is charged with positive charges, then the positive charges escape through the second protection element
28
to the p-type substrate
12
by way of the forward biased p
+
-well diode and pn junction leakage current between the n-well
30
and the p-type substrate
12
.
The conventional protection element for a gate oxide film does not exhibit a sufficient protection performance against plasma damage and cannot completely prevent plasma damage by plasma processes. The inventor of the present invention has discovered that this arises from the following reasons.
The reasons are described in the case of an NMOS transistor formed on a p-type substrate described above with reference to FIG.
1
. The first reason is that, although negative charges can easily escape to the p-type substrate
12
through the n
+
/p-well diode
24
, positive charges cannot completely escape to the p-type substrate
12
through the p
+
-well diode
28
.
By the time the device fabrication is completed, the n-well
30
should be connected to a wire for positive power supply, Vdd, through an n
+
diffusion region
34
in order to prevent a p
+
-well diode
28
from being forward biased during normal device operation. However, during the fabrication process of the NMOS transistor
10
, the n-well
30
is not electrically biased, and thus the n-well
30
is in a floating state with respect to the p-type substrate. Thus, accumulated positive charges during the plasma processes flow through the second protection element
28
by way of the forward biased p
+
-well diode and pn junction leakage current between the n-well
30
and the p-type substrate
12
. The forward biased p
+
-well diode has a low resistance and therefore positive charges can flow easily to the n-well. However, the pn junction between the n-well
30
and the p-type substrate
12
has extremely large resistance because the junction is reverse biased and thus current conduction is done by a very low leakage current that flows as generation-recombination current, which is determined by the area of the n-well
30
.
To effectively let the accumulated charges escape through the second protection element
28
, it is required to make the area of the n-well
30
greater than a certain value. While it is also required to decrease the area of the n-well
30
since a MOS transistor with smaller layout area is preferable. Thus it is difficult to satisfy both of the requirements.
The second reason is that a specific guideline is not available for determining the area of the n-well
30
necessary to fully prevent plasma damage. In addition, no study for enhancing the effect of protection elements has been done.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that has a sufficient device protection function, and enables a circuit layout with high density.
In order to attain the object described above, according to the present invention, there is provided a semiconductor device, comprising a semiconductor substrate of a first conductivity type, a well region of the first conductivity type formed on the semiconductor substrate, a MOS transistor of a second conductivity type formed in the well region of the first conductivity type, a well region of the second conductivity type formed adjacent the well region of the first conductivity type, and a first protection element and a second protection element connected to a gate electrode of the MOS transistor, the first protection element being a pn junction type diode formed from the well region of the first
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