Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-09-19
2004-07-13
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C438S011000, C438S014000
Reexamination Certificate
active
06762433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a mask exposure method used in the production of semiconductor devices. This invention also relates to a reticle mask used in the method. This invention further relates to a semiconductor product wafer produced by the method. This invention also relates to a method of producing semiconductor device chips.
2. Description of Related Art
Semiconductor devices, such as semiconductor integrated circuits, are generally produced by repeatedly exposing a semiconductor wafer through a mask pattern on a reticle using an exposing apparatus, such as a stepper, thereby forming a plurality of exposed areas arranged on the entire surface of the semiconductor wafer. The image of the mask pattern is printed on a resist layer applied on the surface of the semiconductor wafer, and developed to form a resist pattern, which is used as a mask for, for example, etching a layer formed on the surface of the wafer. By repeating these processes, a plurality of semiconductor device chips is produced on entire surface of the wafer. The semiconductor devices chips are separated into individual semiconductor devices at scribe lines between the chips and encapsulated into packages.
Typically, a reduction-type exposing apparatus is used to expose semiconductor wafers. Therefore, the size of the mask patterns on the reticle is several times the size of the actual semiconductor device patterns formed on the semiconductor wafer.
In addition to these actual devices, test devices for measuring electrical characteristics are also formed on semiconductor wafers. These test devices are called test element groups (TEGs) and are formed, for example, in the scribe lines.
Japanese Unexamined Patent Application Publication Nos. 5-291106 and 10-312049 disclose exposure processes of chip patterns. In these processes, a semiconductor chip pattern (LSI pattern) and a TEG pattern are arranged on the same reticle. Required positions of the wafer are exposed through the TEG pattern and the other positions are exposed through the chip pattern. To expose through the TEG pattern, mask blinds of the stepper cover the chip pattern on the reticle so that only the TEG pattern is projected onto the wafer. The TEG pattern is covered to expose through the chip pattern.
A serious concern in semiconductor production is to increase the number of semiconductor device chips produced on one semiconductor wafer. A countermeasure is narrowing the scribe lines. This method is particularly effective in producing semiconductor devices with small chip dimensions, such as 1 mm×1 mm. A plurality of mask patterns for such small semiconductor device chips are closely arranged with narrow scribe lines of, for example, 50 &mgr;m (the width when exposed on the wafer) on the same reticle so that the size of the entire mask pattern substantially corresponds to a field size, for example, 20 mm×20 mm that can be exposed at once by the exposing apparatus. The number of the chips formed by an exposure step and the total number of the chips formed on the entire wafer can be increased. Because the TEG patterns and alignment marks for the exposing apparatus cannot be included within the width of such narrow scribe lines, regions corresponding to one to several semiconductor chips on the mask pattern are allocated to the TEG patterns and the alignment marks.
When the above exposure step, however, is repeated over the entire surface of the semiconductor wafer, a plurality of exposed areas, each composed of a device region including a plurality of semiconductor device chips and a TEG region, is formed on the semiconductor wafer. In order to increase the number of the device chips produced on one wafer, it is preferable that the number of the TEG regions on one wafer be minimized as much as possible, for example, to one to several, by producing the TEG regions in only specific positions.
In the above-described process using the mask blinds, however, the step pitch in the exposed areas arranged on the wafer surface cannot be maintained constant, when the device region and the TEG region have different sizes.
Thus, the distances between alignment marks for use in a laser-trimming step, each provided at a specific position in each device region, are different. Therefore, the laser-trimming step requires complicated treatment, such as combining a plurality of map layouts, or splitting in a plurality of steps on each wafer. Moreover, 5 to 10% of the chips on the periphery of the wafer cannot be treated depending on the laser-trimming apparatuses. A process for measuring electrical characteristics is also complicated due to the irregular distances between the TEG regions.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an exposure method capable of arranging exposed areas with fixed pitches even when TEG regions are formed only at several positions on a semiconductor wafer.
It is another object of this invention to provide a reticle mask used in the exposing method.
According to one aspect of this invention, an exemplary method of fabricating semiconductor devices comprises: applying a resist layer on a surface of a semiconductor wafer; forming a plurality of exposed areas in the resist layer arranged in rows and columns with fixed pitches, the exposed areas including a plurality of first exposed areas each including a device region, and at least one second exposed area including a portion of the device region and a TEG region.
Preferably, the device region of the first exposed areas includes a predetermined number of rows of exposed device chip patterns and the portion of the device region of the second exposed area includes a number of rows of the exposed device chip patterns that is less than the predetermined number of rows.
Preferably, each of the first exposed regions is formed by a single exposure.
Preferably, the first and the second exposed areas are formed using a common reticle having a device pattern region to form the device region and a having TEG pattern region to form the TEG region.
Preferably, the second exposed area is formed by a first exposure of the resist layer through a portion of the device pattern region and by a second exposure of the resist layer through the TEG pattern region of the common reticle.
Preferably, the TEG pattern region of the common reticle includes a blank zone, and a defective pattern formed by the first exposure is erased by the second exposure through the blank zone, or the second exposure through the blank zone prevents formation of a defective pattern by the first exposure.
Preferably, at least one of the first exposed areas is formed by exposing the resist layer through both the device pattern region and the TEG region of the common reticle so that the TEG region of the second exposed area adjacent to the at least one of the first exposed areas is formed simultaneously.
According to another aspect of this invention, an exemplary method of fabricating semiconductor devices comprises: setting a reticle having a device pattern region and a TEG pattern region in an exposing apparatus; positioning a semiconductor wafer having a resist layer on the semiconductor wafer in the exposing apparatus; and forming an exposed area in the resist layer by a first exposure through a portion of the device pattern region of the reticle and by a second exposure through the TEG pattern region of the reticle, wherein a defective pattern formed by the first exposure is erased by the second exposure, or the second exposure prevents formation of a defective pattern by the first exposure.
Preferably, the TEG pattern region of the reticle includes a blank zone and the second exposure though the blank zone erases or prevents the formation of the defective pattern.
Preferably, the device pattern region of the reticle includes a predetermined number of rows of device chip patterns and the portion of the device pattern region includes a number of rows of the device chip patterns that is less than the predetermined number of rows and a p
Kawasaki Microelectronics Inc.
Le Dung A.
Oliff & Berridg,e PLC
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