Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-06-01
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06303395
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to techniques for semiconductor wafer processing.
BACKGROUND OF THE INVENTION
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Integrated circuits are typically fabricated from semiconductor wafers in a process consisting of a sequence of processing steps. This process, usually referred to as wafer fabrication or wafer fab, includes such operations as oxidation, etch mask preparation, etching, material deposition, planarization and cleaning.
A summary of an aluminum gate PMOS (p-channel metal oxide semiconductor transistor) wafer fab process
40
is schematically shown in
FIG. 1
, illustrating major processing steps
41
through
73
, as described in W. R. Runyan et al.,
Semiconductor Integrated Circuit Processing Technology
, Addison-Wesley Publ. Comp. Inc., p.48, 1994. Each of these major processing steps typically include several sub steps. For example, a major processing step such as metallization to provide an aluminum layer by means of sputter deposition in a wafer fab chamber is disclosed in U.S. Pat. No. 5,108,570 (R.C. Wang, 1992). This sputter deposition process is schematically shown in sub steps
81
through
97
of process
80
, see FIG.
2
.
FIGS. 1 and 2
show sequential wafer fab processes. It is also known to utilize wafer fab sub systems which provide parallel processing steps. Such sub systems typically include one or more cluster tools. A cluster tool as defined herein includes a system of chambers and wafer handling equipment wherein wafers are processed in the cluster tool chambers without leaving a controlled cluster tool environment such as vacuum. An example of a cluster tool is disclosed in U.S. Pat. No. 5,236,868 (J. Nulman, 1993) which employs a vacuum apparatus having a central chamber and four processing chambers. A wafer handling robot in the central chamber has access to the interior of each the processing chambers in order to transfer wafers from the central chamber into each of the chambers while keeping the wafers in a vacuum environment. In one example, wafers in the '868 cluster are first transferred for processing to a cleaning chamber, then to a PVD (physical vapor deposition) chamber, followed by transfer to an annealing chamber and subsequently to a degassing chamber, thus utilizing a sequential process. It is also known to use cluster tools such as those disclosed in the '868 patent to process wafers in chambers which are used in parallel. For example, if a slow processing step is followed by a fast processing step, three chambers can be used in parallel for the slow process while the fourth chamber is used for the fast process.
It is well known to those of ordinary skill in the art that one or more processing parameters of a typical wafer fab process step need to be controlled within a relatively narrow range in order to obtain a product which has the desired characteristics. For example, U.S. Pat. No. 5,754,297 (J. Nulman, 1998) discloses a method and apparatus for monitoring a deposition rate during wafer fab metal film deposition such as sputtering. The '297 patent teaches that the metal deposition rate decreases with increasing age of the sputter target if the input sputter power level is maintained at a constant level. As a consequence, critical processing characteristics, such as the metal deposition rate, may vary from run to run for a given wafer fab processing chamber in ways that can affect the yield and quality of devices processed in that chamber. As disclosed in the '297 patent, the deposition system can be more readily maintained near desired levels when processing variables, such as the power input to the sputtering source, are adjusted in response to observed variations in the metal deposition processing characteristics. This requires in-situ measurement of processing characteristics, using for example a deposition rate monitor based on the optical attenuation of light passing through the deposition environment, thereby detecting the rate at which material is flowing from the deposition source to the deposition substrate, as described more fully in the '297 patent.
Advances in semiconductor materials, processing and test techniques have resulted in reducing the overall size of the IC circuit elements, while increasing their number on a single body. This requires a high degree of product and process control for each processing step and for combinations or sequences of processing steps. It is thus necessary to control impurities and particulate contamination in the processing materials such as process gases. Also, it is necessary to control processing parameters such as temperature, pressure, gas flow rates, processing time intervals and input sputter power, as illustrated in the '570 and '297 patents. As illustrated in
FIGS. 1 and 2
, a wafer fab includes a complex sequence of processing steps wherein the result of any particular processing step typically is highly dependent on one or more preceding processing steps. For example, if there is an error in the overlay or alignment of etch masks for interconnects in adjacent IC layers, the resulting interconnects are not in their proper design location. This can result in interconnects which are packed too closely, forming electrical short defects between these interconnects. It is also well known that two different processing problems can have a cumulative effect. For example, a misalignment of interconnect etch masks which is not extensive enough to result in an electrical short, can still contribute to causing an electrical short if the process is slightly out of specification for allowing (or not detecting) particulate contamination having a particle size which would not have caused an electrical short if the interconnect masks had been in good alignment.
Processing and/or materials defects such as described above generally cause a reduced wafer fab yield, wherein the yield is defined as the percentage of acceptable wafers that are produced in a particular fab. In-process tests and monitoring of processing parameters are utilized to determine whether a given in-process product or process problem or defect indicates that intervention in the process run is necessary, such as making a processing adjustment or aborting the run. Consequently, product and process control techniques are used extensively throughout a wafer fab. When possible, yield problems are traced back to specific product or processing problems or defects to ultimately improve the yield of the wafer fab. High yields are desirable for minimizing manufacturing costs for each processed wafer and to maximize the utilization of resources such as electrical power, chemicals and water, while minimizing scrap re-work or disposal.
It is known to use SPC (statistical process control) and SQC (statistical quality control) methods to determine suitable wafer fab control limits and to maintain the process within these limits, see for example R. Zorich,
Handbook Of Quality Integrated Circuit Manufacturing
, Academic Press Inc., pp. 464-498, 1991. SPC and SQC methodologies suitable for a wafer fab include the use of control charts, see for example R. Zorich at pp. 475-498. As is well known to those of ordinary skill in the art, a control chart is a graphical display of one or more selected process or product variables, such as chamber pressure, which are sampled over time. The target value of a particular variable and its upper and lower control limits are designated on the chart, using well known statistical sampling and computation methods. The process is deemed out of control when the observed value of the variable, or a statistically derived value such as the average of several observed values, is outside the previ
Applied Materials Inc.
Dalhuisien Albert J.
Niebling John F.
Stevenson André C
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