Semiconductor processing method of reducing an etch rate of...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S723000, C438S743000, C438S618000, C438S637000

Reexamination Certificate

active

06194319

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor processing method of reducing an etch rate of one portion of a doped material relative to another portion, and methods of forming openings, such as, for example, methods of forming openings in doped materials.
BACKGROUND OF THE INVENTION
Integrated circuitry typically comprises electrical interconnections. A typical semiconductor electrical connection includes a metal or other conductive layer communicating with other layers located at different elevations within a substrate. Forming electrical interconnections is typically conducted, in part, by etching an opening through insulating material, and then flowing metal or other conductive material to within the opening.
An exemplary semiconductor structure comprises a bulk monocrystalline silicon substrate with an overlying silicon dioxide layer as the insulating material, such as borophosphosilicate glass (BPSG). BPSG can be considered to be silicon dioxide doped with phosphorus and boron. An opening can be formed through the BPSG layer and to the underlying substrate with a suitable etch. After etching through the BPSG layer to form the opening, the silicon substrate is exposed to the environment, routinely including oxygen. Silicon reacts with oxygen to form an oxide, specifically silicon dioxide, a material having insulative properties. Accordingly, a film of silicon dioxide, commonly referred to as native oxide, forms on the exposed silicon. If the native oxide is not removed, the conductive properties of an electrical connection formed within the opening can be diminished.
Typically, the native oxide is removed by an etching process, preferably an oxide etch. However, because the BPSG layer is also an oxide and defines the sidewalls of the opening, the sidewalls will etch during removal of the native oxide. The etching of the sidewalls can widen the opening. Moreover, because doped materials etch faster than less doped materials, and because BPSG is essentially a doped oxide, the sidewalls will etch faster than the native oxide. This etch rate differential increases the difficulty to fabricate and control the width dimensions of a opening. With the emphasis in the semiconductor industry to increase the density of active components per unit area of semiconductor substrate, it is typically desired to keep openings narrow. It would, therefore, be desirable to develop improved methods of forming openings in doped substrates.
SUMMARY OF THE INVENTION
In one aspect, the invention includes a semiconductor processing method of selectively reducing an etch rate of a doped material. At least some dopant is removed from one portion of the doped material while leaving the dopant in an other portion of the doped material.
In another aspect, the invention includes a semiconductor processing method of forming openings. A doped material is provided over a substrate. Openings are etched in the doped material. Dopant in the doped material proximate the openings is depleted relative to other regions of the doped material.
In yet another aspect, the invention includes a semiconductor processing method of forming openings. A doped material is provided over a substrate and openings are formed in the doped material. The doped material has a substantially uniform dopant concentration throughout its thickness. One peripheral portion of the openings is defined by the doped material and another peripheral portion is defined by another material. The dopant concentration is depleted from the doped material at the peripheral portion. After the depleting, the peripheral portions of the openings are subjected to an etch to remove the other material.


REFERENCES:
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patent: 5420056 (1995-05-01), Moslehi
patent: 5731130 (1998-03-01), Tseng
patent: 5804515 (1998-09-01), Park
patent: 5981376 (1999-11-01), Komatsu et al.
patent: 6013547 (2000-01-01), Liaw
patent: 6022798 (2000-02-01), Sumi et al.

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