Semiconductor processing employing a semiconductor spacer

Details Semiconductor processing employing a semiconductor spacer Semiconductor processing employing a semiconductor spacer

1999-09-22

2003-11-04

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S304000, C438S564000, C438S542000, C438S558000, C438S683000

Reexamination Certificate

active

06642134

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and to a method of manufacturing a semiconductor device. The present invention has particular applicability in manufacturing high density CMOS semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing techniques.
As device features continually shrink in size, it becomes necessary to decrease the depth of the source/drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate having a width of about 0.25 microns, the junction depth (X
j
) should be no greater than about 2000 Å.
In conventional semiconductor methodology illustrated in
FIG. 1
, an initial gate dielectric layer
12
, such as silicon oxide, is formed on semiconductor substrate
10
and a gate electrode layer formed thereon as in conventional practices. The gate electrode layer, typically doped polysilicon, is etched in a conventional manner to form a gate electrode
14
on underlying gate oxide layer
12
.
Next insulating sidewall spacers
16
are formed on each side surface of get electrode
14
and underlying dielectric layer
12
adjacent gate electrode
14
side surfaces, as shown in FIG.
2
. Sidewall spacers
16
are formed by depositing a layer of dielectric material, such as a silicon nitride or silicon oxide, and anisotropically etching, thereby exposing the surface of semiconductor substrate
10
adjacent sidewall spacers
16
. Subsequently, using gate electrode
14
and sidewall spacers
16
as a mask, impurities are ion implanted, as indicated by arrows
19
in
FIG. 2
, to form source/drain implants
18
. Next, activation annealing is performed to form source/drain regions in substrate
10
.
A metal, such as titanium, is then sputtered across the semiconductor. A low temperature anneal follows to create a high-resistivity titanium silicide (TiSi
x
) on the exposed silicon of gate electrode
14
and over source/drain regions
18
. The unreacted titanium over spacers
16
is then removed, followed by a high temperature anneal to form a low-resistivity TiSi
x
, as indicated by XXX's in FIG.
2
.
A drawback attendant upon the formation of the titanium silicide is that silicon in semiconductor substrate
10
is consumed in the titanium-silicon reaction This, combined with the shallow junctions depths desired in semiconductor devices having design features of 0.25 microns and under, can lead to the suicide shorting through source/drain junctions
18
. When such shorting occurs, circuit reliability is adversely affected, possibly leading to circuit failure.
SUMMARY OF THE INVENTION
There exists a need for a method of manufacturing a CMOS device which avoids suicide shorting through the source/drain junctions.
There is also a need for a semiconductor device with increased reliability.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device including a semiconductor substrate and a dielectric layer formed on the semiconductor substrate. The semiconductor device also includes a gate electrode having an upper surface and side surfaces formed on the dielectric layer and first sidewall spacers formed on the side surfaces of the gate electrode. The semiconductor device further includes second sidewall spacers comprising a semiconducting material that are formed on the first sidewall spacers.
Another aspect of the present invention is a method of manufacturing a semiconductor device. The method includes forming a dielectric layer on a surface of a semiconductor substrate and forming a conductive layer on the dielectric layer. The method also includes patterning the conductive layer to form a gate electrode having an upper surface and side surfaces, depositing an insulating layer and etching the insulating layer to form first sidewall spacers on the side surfaces of the gate electrode. The method further includes depositing a semiconducting layer and etching the semiconducting layer to form second sidewall spacers on the first sidewall spacers.


REFERENCES:
patent: 5407847 (1995-04-01), Hayden et al.
patent: 5710054 (1998-01-01), Gardner et al.
patent: 5759885 (1998-06-01), Son
patent: 5824586 (1998-10-01), Wollesen et al.
patent: 6037232 (2000-03-01), Wieczorek et al.
patent: 6165900 (2000-12-01), Kim et al.
patent: 6180477 (2001-01-01), Liao

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