Semiconductor process yield analysis based on evaluation of...

Details Semiconductor process yield analysis based on evaluation of... Semiconductor process yield analysis based on evaluation of...

2005-04-26

2005-04-26

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Quality evaluation

C702S085000, C438S014000

Reexamination Certificate

active

06885955

ABSTRACT:
Semiconductor process yield analysis in which the relationship between a wafer-level parameter and a die-level parameter is evaluated can be performed more quickly and with greater accuracy than has been the case with previous such yield analysis. The yield analysis can be performed by selecting regions of a semiconductor wafer or wafers from which parametric data is to be obtained for use in the analysis, based on one or more characteristics of the wafer(s). The yield analysis can be performed by grouping the parametric data based on both a grouping of the wafer-level parametric data and a grouping of the die-level parametric data. The yield analysis can be performed by grouping the parametric data in greater than 3 groups.

REFERENCES:
patent: 6210983 (2001-04-01), Atchison et al.
patent: 6324481 (2001-11-01), Atchison et al.
patent: 6393602 (2002-05-01), Atchison et al.
patent: 20030229410 (2003-12-01), Smith et al.

Affiliated with

Also associated with

Rating

Semiconductor process yield analysis based on evaluation of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor process yield analysis based on evaluation of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor process yield analysis based on evaluation of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3417847