Semiconductor process with deuterium predominance at high temper

Details Semiconductor process with deuterium predominance at high temper Semiconductor process with deuterium predominance at high temper

1998-07-28

2000-11-07

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438585, H01L 213205

Patent

active

061436348

ABSTRACT:
Channel-hot-carrier reliability can be improved by deuterium passivation of the gate interface. By performing high temperature steps (above 300 degrees Celsius) in a deuterium-containing ambient, harmful depletion of deuterium due to diffusion away from the gate interface is avoided.

REFERENCES:
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5972765 (1999-10-01), Clark et al.
Deuterium Post-Metal Annealing of MOSFET's for Improved Hot Carrier Reliability, IEEE Electron Device Letters, vol. 18, No. 3, Mar. 1997, pp. 41-43.

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