Semiconductor process using delay-compensated exposure

Details Semiconductor process using delay-compensated exposure Semiconductor process using delay-compensated exposure

2005-03-15

2005-03-15

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Including control feature responsive to a test or measurement

C355S053000

Reexamination Certificate

active

06866974

ABSTRACT:
A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.

REFERENCES:
patent: 6447964 (2002-09-01), Okino et al.

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