Semiconductor process for removing defects due to edge chips...

Details Semiconductor process for removing defects due to edge chips... Semiconductor process for removing defects due to edge chips...

2006-07-19

2009-10-06

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S238000, C438S381000, C257SE21170, C257SE21229, C257SE21304, C257SE21231, C257SE21646

Reexamination Certificate

active

07598180

ABSTRACT:
A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.

REFERENCES:
patent: 7101752 (2006-09-01), Park et al.
patent: 2002/0187598 (2002-12-01), Park et al.
patent: 2006/0244032 (2006-11-01), Park et al.
patent: 2000-306795 (2000-11-01), None
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Ruzyllo, Jerzy; “Semiconductor Glossary”; 2004; Prosto Multimedia Publishing; First Edition; p. 50.

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