Semiconductor process

Details Semiconductor process Semiconductor process

2009-08-26

2011-11-22

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S701000

Reexamination Certificate

active

08062972

ABSTRACT:
A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.

REFERENCES:
patent: 6465352 (2002-10-01), Aoki
patent: 6797627 (2004-09-01), Shih et al.
patent: 7192878 (2007-03-01), Weng et al.
patent: 7199059 (2007-04-01), Cheng et al.
patent: 7628866 (2009-12-01), Lin et al.
patent: 2009/0142931 (2009-06-01), Wang et al.
A. Matsushita, N. Ohashi, K. Inukai, H.J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, and N. Kobayashi, “Low Damage Ashing using H2/He plasma for Porous Ultra Low-k”, 2003, pp. 147-149, Research Dept. 2, Semiconductor Leading Edge Technologies, Inc., Japan.

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