Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-09-24
2003-09-09
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020
Reexamination Certificate
active
06617870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor probe station, and, more particularly, to a semiconductor probe station including a cooling system and method thereof. The present invention additionally relates to an Electrical Die Sorting process (EDS) using the probe station for testing integrated chips on a semiconductor wafer.
2. Description of the Related Art
Typically, a plurality of integrated chips are formed on a semiconductor wafer through an array of fabrication processes including Oxidation, Chemical Vapor Deposition, Metallization, etc. After fabrication, an EDS method is carried out to examine the electrical state of each chip. Chips that fail are sorted out from chips that pass.
The EDS process is performed on a probe station having a probe chuck being capable of moving along a z-axis driven by driving source. The probe station temperature can be varied from a normal room temperature of about 25 to 35° C. to a high temperature of about 80 to 90° C. A plurality of vacuum holes are provided on a probe station surface for forming a vacuum by absorbing air from outside the probe station. In addition, a probe card is provided a predetermined distance from the probe chuck. The probe card has a plurality of needles that are applied to pads on the chip thereby transferring electrical signals to the circuit of each chip formed on the semiconductor wafer.
The EDS process comprises mounting a wafer having a plurality of chips formed thereon on the probe chuck, raising the temperature of the probe chuck to about 80 to 90° C., and contacting a needle of the probe card with the chip pad on the wafer. The chip is then tested by applying a predetermined electrical current level. The chips that fail are then separated or sorted from the chips that pass the EDS process. The failed chips are sorted into two groups: chips that can be repaired and chips that cannot be repaired.
Based on the EDS data, chips that can be repaired go through a Laser-repair process that utilizes a laser beam to repair the failed chips. The wafer that goes through the Laser-repair process is then placed on the probe chuck. The wafer temperature is allowed to naturally fall to normal room temperature of about 25 to 35° C. After the temperature on the probe chuck cools, the wafer then goes through a Post-repair process for testing the operating state of the repaired chips. The Post-repair process involves contacting the needle of the probe card with the chip pad of the wafer. Thus, the probe chuck in the Pre-laser process is at a high temperature. The probe chuck in the Post-laser process is at a normal room temperature.
The water goes through a Back-grinding process for grinding the back side of the wafer as it goes through the Post-laser process. Thereafter, the wafer goes through an Inking process for identifying the failed chips on the wafer by marking them with ink. The ink on the failed chips is dried by passing through a bake oven. Then, the wafer goes through a Slicing process in which the passing chips are assembled.
The above-described EDS process has an inherent disadvantage. Namely, the Pre-laser process is carried out when the probe chuck is at a high temperature and the Post-laser process is carried out when the probe chuck is at a room temperature. It generally takes between 45 minutes and three hours to bring the chuck temperature down to room temperature. The cooling time varies with the facility used to reduce the temperature of the probe chuck. Accordingly, a need remains for a probe station that improves the efficiency and the productivity of the EDS process.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with prior art probe stations and cooling systems and methods thereof.
It is another object of the present invention to provide an EDS method that is efficient and productive.
A semiconductor probe station for carrying out an Electronic Die Sorting (EDS) process is provided. The probe station comprises a frame having a top, bottom, back, and front sides and ends; a platen positioned on the top side of the frame; a forcer positioned on the platen including a moving means for moving the forcer along an x-axis and y-axis; a probe chuck attached to the forcer for mounting a wafer, the probe chuck moving along a z-axis; and a cooling system for cooling the probe chuck. The semiconductor probe station further includes a quick loader installed on the top side of the frame for loading the wafer; a manual loader installed on the top side of the frame for manually loading the wafer; a flat zone aligner installed on the top side of the frame for aligning the wafer; and a transfer arm installed on the top side of the frame for transferring the wafer from a carrier to the quick loader. The semiconductor probe station further includes an air supply line coupled to an air source; an supplier coupled to the air supply line, the air supply line transferring pressurized air from an air source to the air supplier and the air supplier transferring the received pressurized air to the probe chuck. The cooling system is mounted on the back side of the frame and is supported by a bracket.
A cooling system for a semiconductor probe station is provided. The cooling system comprises an air source for supplying pressurized air; an air supplier having a plurality of nozzles; an air supply line coupled at a first end to the air source and at a second end to the air supplier for transferring the pressurized air from the air source to the air supplier. A plurality of air openings are provided on one end of each of the plurality of nozzles. The plurality of nozzles is aligned along a first direction. The air supplier includes a first and a second end nozzles having an angled air exit such that the pressurized air is centrally directed. The air supply line includes a solenoid valve for opening and closing the air supply line responsive to an applied voltage. The air supply line includes a filter coupled to the solenoid valve for filtering the pressurized air and a first and a second portion, the first portion having a diameter larger than a diameter of the second portion and the solenoid valve being connected between the first and second portions.
The cooling system includes a first divergence line having a first and a second end, the first end connected to a first end of the air supplier; a second divergence line having a first and a second end, the first end connected at a second end of the air supplier; and a t-shaped line having a first, second, and third ends, the first end of the t-shaped line connected to the second end of the first divergence line, the second end of the t-shaped line connected to the second end of the second divergence line, and the third end of the t-shaped line connected to the air supply line. The air source provides pressurized air having a pressure between 110 and 115 pounds per square inch.
A method for cooling a semiconductor probe station is provided. The probe station comprises a frame having a top, bottom, front, and back sides and ends, a cooling system mounted on the back side of the frame, a vacuum system mounted on the frame, and a probe chuck mounted on the top side of the frame. The method for cooling comprises moving a forcer mounted on the top side of the frame close to the cooling system by a moving means; moving the probe chuck along a z-axis; and cooperatively operating the vacuum and cooling systems to lower a temperature of the probe chuck for a predetermined time. Cooperatively operating the vacuum and cooling systems includes operating the vacuum and cooling systems until the temperature of the probe chuck is between 30° C. and 31° C.
The method further includes applying a post-laser process to a wafer on the probe chuck after the temperature on the probe chuck is lowered and applying a pre-laser process to a wafer on the probe chuck after the temperature on the probe chuck is lowered. The method includes moving the forcer to closer to the cooling system after
Kim Jae-gyu
Ko Young-nam
Lee Jong-hoon
Shin Yu-kwang
Marger Johnson & McCollom PC
Nguyen Vinh P.
Samsung Electronics Co,. Ltd.
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