Semiconductor planarization process

Details Semiconductor planarization process Semiconductor planarization process

1987-05-13

1988-01-26

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156663, 252 793, 252 794, 4273762, 437228, 437235, B44C 122, C03C 1500, C03C 2506

Patent

active

047215488

ABSTRACT:
Planarization process for planarizing glass layer which receives first layer metal. Spin-on-glass is cured in steam and then etched back using hydrofluoric and nitric acids diluted in acetic acids.

REFERENCES:
patent: 4539744 (1985-09-01), Burton
patent: 4634494 (1987-01-01), Taji et al.
patent: 4676867 (1987-06-01), Elkins et al.

Affiliated with

Also associated with

Rating

Semiconductor planarization process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor planarization process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor planarization process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1467017