Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2003-01-15
2004-07-27
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S783000, C438S118000, C438S617000
Reexamination Certificate
active
06768212
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and to methods for manufacturing such semiconductor packages.
BACKGROUND OF THE INVENTION
As die sizes increase to include more components (e.g., circuits, transistors, or the like) to provide more functions, and semiconductor package sizes decrease to reduce size and promote a miniaturization of semiconductors, semiconductor packaging manufacturers must contend with reduced operating margins on the substrate between a die attachment area of the substrate, a stitch bond area of the substrate, and a die that is placed on the die attachment area of the substrate. Semiconductor packages may comprise a substrate, which includes a die attachment area for receiving a die, and a stitch bond area adjacent to the die attachment area. The stitch bond area forms a surface for connecting a lead wire from a die to electrical conductors on the substrate, thereby forming an electrical connection between the die and the conductors or conductive balls in the case of a ball grid array on the substrate. The term substrate as used herein may be a lead frame, a laminate substrate, a tape base substrate, or the like. Further, a die attachment material, e.g., a die attachment paste, a die attachment film, or the like, may be placed on a die attachment area of the substrate for securing a die thereto. In known semiconductor packages, the die attachment material may bleed out of the die attachment area when a die is affixed to the die attachment area. Moreover, the die attachment material which bleeds out of the die attachment area may contact or cover the stitch bond area which is adjacent to the die attachment. Such contact may prevent or hinder attachment of wire leads, from the die to the substrate. As a result, an electrical connection may not be formed adequately between the die and the conductors on the substrate. To compensate for the tendency of die attachment material to bleed out from the die attachment area onto the stitch bond area, manufacturers have to reduce the size of a die that is attached to a given die attachment area, or manufacturers have to increase the die attachment area of the substrate for a given die, or both.
A still further problem is that the gold wire used for attaching to the substrate conductors or balls may not easily connect to the lead frame metal conductors or balls in the ball grid array case. This may be due to the conductor material and/or the size of the wire attachment area.
REFERENCES:
patent: 4771330 (1988-09-01), Long
patent: 4907734 (1990-03-01), Conru et al.
patent: 5328079 (1994-07-01), Mathew et al.
patent: 5647942 (1997-07-01), Haji
patent: 6079610 (2000-06-01), Maeda et al.
patent: 6321976 (2001-11-01), Lo et al.
patent: 2003/0166333 (2003-09-01), Takahashi
Kadoguchi Sohichi
Karashima Akira
Simmons-Matthews Margaret
LandOfFree
Semiconductor packages and methods for manufacturing such... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor packages and methods for manufacturing such..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor packages and methods for manufacturing such... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3232847