Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-10-09
2003-01-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S787000, C438S123000
Reexamination Certificate
active
06512286
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and methods for fabricating the same, and more particularly, to a semiconductor package, in which a die pad of a lead frame acts as a chip carrier with an opening formed in the die pad, and a method for fabricating the semiconductor package.
BACKGROUND OF INVENTION
A semiconductor package with a lead frame acting as a chip carrier generally has the following drawbacks. First, a die pad of the lead frame is dimensionally large in surface area. Moreover, the die pad is in poor adherence with an encapsulant encapsulating a chip disposed on the die pad. This tends to cause delamination between the die pad and the encapsulant during temperature variation in a reliability test or practical operation, and therefore deteriorates reliability and quality of he semiconductor package. Further, as the chip is attached in larger area to the die pad, thus the chip suffers greater thermal stress generated from the die pad during a temperature cycle in a fabrication process. This easily makes the chip crack or delaminated from the die pad.
In order to eliminate the foregoing drawbacks, U.S. Pat. No. 5,233,222 proposes a semiconductor package with a die pad having an opening, as shown in FIG.
3
A. The semiconductor package
3
has a die pad
30
formed with an opening
300
therein. A chip
31
is attached to the die pad
30
via silver paste
32
in a manner that, the chip
31
covers the opening
300
, and a bottom side
310
of the chip
31
is partially exposed to outside of the opening
300
. This significantly decreases the attachment area between the chip
31
and the die pad
30
, and thus effectively reduces thermal stress generated by the die pad
30
to the chip
31
, so that delamination between the die pad
30
and the chip
31
and cracking of the chip
31
can be prevented. Moreover, in the provision of the opening
300
, adherence between the die pad
30
and an encapsulant
33
encapsulating the chip
31
can be further improved. Similarly, U.S. Pat. No. 5,327,008 also proposes a semiconductor package with a die pad of a X-like shape, in an effort to reduce attachment area between a chip and a die pad. As improvements rendered by this latter patent are similar to those depicted in the above former patent, thus the latter patent is not illustrated with reference to a drawing.
As described above, the foregoing two U.S. patents have several drawbacks; however, the silver paste for attaching the chip to the die pad needs to be applied in a precisely controlled amount. As shown in
FIG. 3B
, if the silver paste
32
is used in excess, excess silver paste
32
leaks downwardly through a periphery of the opening
300
of the die pad
30
, and thus contaminates the semiconductor package. Further, as the silver paste
32
has a high coefficient of thermal expansion (CTE) of about 80 ppm, thus delamination occurs between the encapsulant
33
and the silver paste
32
due to CTE dismatch. As shown in
FIG. 3C
, if the silver paste
32
is used in an insufficient amount, a gap
301
is easily formed between the chip
31
and the die pad
30
at the periphery of the opening
300
. In a molding process for forming the encapsulant
33
, a molding resin can not completely fill up the gap
301
, and thus voids are formed, thereby making the chip
31
easily crack at positions corresponding to the voids. As a result, the delamination or void formation detrimentally affects reliability and quality of the semiconductor package. However, precisely controlling the usage amount of the silver paste increases costs and complexity in fabrication, and is substantially difficult to perfectly implement.
Therefore, in order to solve the foregoing problems, U.S. Pat. Nos. 4,942,452 and 5,150,193 each proposes a semiconductor package with a die pad formed with a groove thereon. As shown in
FIG. 4
, the semiconductor package
4
has a die pad
40
formed with a groove
401
in proximity to an opening
400
. The groove
401
is used to prevent silver paste
42
applied in excess on the die pad
40
from flashing to the opening
400
. However, if the silver paste
42
is used in an insufficient amount, a gap
402
between a chip
41
and the die pad
40
can not be completed filled with the silver paste
42
, thereby making voids formed in the gap
402
. As a result, the problem of forming voids still exists.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package and a method for fabricating the same, so as to effectively prevent void formation and flash of silver paste from occurrence.
In accordance with the foregoing and other objectives, the present invention proposes a semiconductor package and a method for fabricating the same. The semiconductor package of the invention comprises: a lead frame having a die pad and a plurality of leads, wherein the die pad is formed with at least one opening therein; a chip attached to the die pad via an adhesive in a manner that, the chip covers on end of the opening and a surface of the chip is partially exposed to the opening, wherein a gap connected to the opening is formed between the chip and the die pad in proximity to the opening; a covering layer formed on the exposed surface of the chip for completely filling the gap, so as to allow air in the gap to be completely dissipated; a plurality of conductive elements for electrically connecting the chip to the leads; and an encapsulant for encapsulating the chip, the die pad, the covering layer, the conductive elements and part of the leads.
The method for fabricating a semiconductor package comprises the steps of: providing a lead frame having a die pad and a plurality of leads, wherein the die pad is formed with at least one opening therein; attaching a chip to the die pad via an adhesive in a manner that, the chip covers on end of the opening and a surface of the chip is partially exposed to the opening, wherein a gap connected to the opening is formed between the chip and the die pad in proximity to the opening; forming a covering layer on the exposed surface of the chip for completely filling the gap, so as to allow air in the gap to be completely dissipated; bonding a plurality of conductive elements between the chip and the leads, so as to electrically connect the chip to the leads; and forming an encapsulant for encapsulating the chip, the die pad, the covering layer, the conductive elements and part of the leads.
The opening in the die pad is not particularly restricted in size and shape, but needs to reduce attachment area between the chip and the die pad and provide sufficient support to the chip.
The gap between the chip and the die pad is formed by applying the adhesive on the die pad for attaching the chip to the die pad in an amount that does not cover area on the die pad in proximity to the opening.
The covering layer can be made of a resin compound good in fluidity such as polyimide resin, and completely fills the gap between the chip and the die pad with air in the gap being completely dissipated, so that no void is formed in the encapsulant after completing a molding process for forming the encapsulant.
REFERENCES:
patent: 4942452 (1990-07-01), Kitano et al.
patent: 5150193 (1992-09-01), Yasuhara et al.
patent: 5233222 (1993-08-01), Djennas et al.
patent: 6057595 (2000-05-01), Pohl et al.
patent: 6087715 (2000-07-01), Sawada et al.
patent: 6144107 (2000-11-01), Narita
patent: 6410979 (2002-06-01), Abe
patent: 6440779 (2002-08-01), Chiu et al.
Lin Yuan-Fu
Tsai Water
Chaudhuri Olik
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Pham Hoai
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