Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
1997-08-13
2001-02-27
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S673000, C257S675000, C257S706000, C257S738000, C257S780000
Reexamination Certificate
active
06194778
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package of a ultra-many-pin structure in which a semiconductor chip is bonded to a novel lead frame, and to a manufacturing method of the lead frame.
FIG. 1
shows a conventional semiconductor package which can be mounted on a printed wiring board or the like through an organic board having external connection terminals such as solder balls.
As shown in
FIG. 1
, a semiconductor chip
51
is mounted on the front surface of a multilayered organic wiring board
50
of about 2 to 6 layers which is made of an organic material. Electrode pads of the semiconductor chip
51
are connected to wiring films
52
that are formed on the front surface of the multilayered organic wiring board
50
by wire bonding, i.e., with gold wires
53
or the like.
The back surface of the multilayered organic wiring board
50
is provided with solder balls (external connection terminals)
55
which are electrically connected to the wiring films
52
on the front surface via through-holes
54
. The solder balls
55
project from openings of a solder resist film
56
. The semiconductor chip
51
is sealed with a sealing resin
57
together with the gold wires
53
.
In the above-configured semiconductor package
58
, the solder balls
55
formed on the back surface are connected to a printed wiring board
59
. In many cases the multilayered organic wiring board
50
is called a ball grind array (BGA) because a number of solder balls
55
are arranged in grid form, and the semiconductor package
58
using the multilayered organic wiring board
50
is called a BGA package.
However, there is a certain limit in reducing the wiring pitch in the conventional semiconductor package
58
, because the electrode pads of the semiconductor chip
51
are connected to the wiring films
52
of the multilayered organic wiring board
50
by wire bonding. In the case of a semiconductor package called TCP (tape carrier package), leads are formed by etching metal foil (copper foil) that is attached to an insulating film. Therefore, also in this case, due to restrictions such as one resulting from lead thinning by side etching, there is a certain limit in increasing the number of pins.
In view of the above, the present assignee has already proposed semiconductor packages of an ultra-many-pin structure in which a semiconductor chip is bonded to a novel lead frame (or lead frame structural body).
FIG. 2
is a side sectional view showing an example of such semiconductor packages of an ultra-many-pin structure.
In the illustrated configuration of a semiconductor package
60
, a plurality of electrode pads
62
are formed on the front surface (chip bottom surface as viewed in
FIG. 2
) of a semiconductor chip
61
along its periphery. A reinforcement plate
63
is provided outside the semiconductor chip
61
so as to surround it, and the reinforcement plate
63
defines a package external shape. A wiring film
65
is laminated on the reinforcement plate
63
through an insulating bonding layer
64
. The wiring film
65
is constituted of a plurality of leads
66
consisting of inner leads
66
a
and outer leads
66
b
and an insulating film
67
which covers and protects the outer leads
66
b
. The tips of the inner leads
66
a
are connected to the electrode pads
62
formed on the chip front surface, and solder balls (external connection terminals)
68
are formed on the outer leads
66
b
so as to penetrate through the insulating film
67
. A peripheral space of the semiconductor chip
61
is charged with a sealing resin
69
, and a radiation plate
71
is bonded to the chip back surface and the reinforcement plate
63
through a heat conductive adhesive
70
.
Now, a manufacturing procedure of the above semiconductor package
60
will be described roughly.
First, to produce a lead frame, a metal base
72
of a three-layer structure is prepared as shown in FIG.
3
A. The metal base
72
has a structure in which an aluminum film
74
is formed on the front surface of a substrate (hereinafter called a copper substrate)
73
made of copper or a copper alloy and a nickel film
75
is formed thereon. Then, as shown in
FIG. 3B
, a plurality of leads
66
are formed on the front surface of the metal base
72
by electrolytic copper plating. Then, as shown in
FIG. 3C
, slits
76
are formed to define a lead frame outer shape for each chip. Then, as shown in
FIG. 3D
, an insulating film
67
is laid on the leads
66
, to form a wiring film
65
constituted of the plurality of leads
66
and the insulating film
67
. At this time, the lead portions projecting from the insulating film
67
become inner leads
66
a
and the lead portions covered with and protected by the insulating film
67
become outer leads
66
b
. Subsequently, as shown in
FIG. 3E
, an undercoat film of nickel, for instance, is formed on the outer leads
66
b
which are covered with the insulating film
67
, and a solder material
68
a
is laid on the undercoat film by electrolytic plating. At this time point, the solder material
68
a
has mushroom shapes.
Thereafter, as shown in
FIGS. 4A and 4B
, the copper substrate
73
, the aluminum film
74
, and the nickel film
75
of the metal base
72
are sequentially removed by selective etching while an outer ring
77
is left, so that the respective leads
66
are separated from and made independent of each other. Then, as shown in
FIG. 4C
, a reinforcement plate
63
is bonded to the surfaces of the outer leads
66
b
which are covered with the insulating film
67
through an insulting bonding layer
64
. Then, as shown in
FIG. 4D
, bumps
78
are formed on the tips of the respective inner leads
66
a
extending from the insulating film
67
.
Thus, a lead frame
79
before attachment of a semiconductor chip is completed.
Thereafter, to attach a semiconductor chip to the above-produced lead frame
79
, the tips of the inner leads
66
a
are connected to electrode pads
62
of a semiconductor chip
61
through the bumps
78
as shown in FIG.
5
A. Subsequently, as shown in
FIG. 5B
, a sealing resin
69
is injected into a peripheral space of the semiconductor chip
61
and then cured. Then, as shown in
FIG. 5C
, a radiation plate
71
is bonded to the back surface of the semiconductor chip
61
and the reinforcement plate
63
through a heat conductive adhesive
70
. Then, as shown in
FIG. 5D
, the solder material
68
a
which was laid by electrolytic plating in the previous lead frame manufacturing process is shaped by causing it to reflow, to obtain desired solder balls
68
. Finally, as shown in
FIG. 5E
, the outer ring
77
is separated with the outer circumference of the reinforcement plate
63
as the boundary, to complete the semiconductor package
60
shown in FIG.
2
.
The semiconductor package
60
realizes an ultra-many-pin structure beyond the previous limit, because the leads
66
can be patterned more finely, which results from the fact that the leads
66
are formed on the metal base
72
by electrolytic copper plating at the stage of manufacturing the lead frame
79
. Further, the semiconductor package
60
is superior in heat dissipation because the radiation plate
71
is bonded to the chip back surface side.
However, even the above ultra-many-pin structure semiconductor package
60
has the following problems:
(1) Stress-induced breakage likely occurs in the bonding portion between the chip front surface and the sealing resin
69
.
(2) The front surface of the semiconductor chip
61
is likely affected by radiations such as &agr;-rays. As a countermeasure, it is necessary to coat polyimide or the like on the chip front surface.
(3) It takes time to charge the peripheral space of the semiconductor chip
61
with the sealing resin
69
.
(4) Crosstalk noise likely occurs when the pattern of the leads
66
is made finer.
(5) The bumps
78
are polluted with a gas generated from the insulating bonding layer
64
when the bumps
78
are formed on the tips of the inner leads
66
a
in the lead frame manufacturing process.
(6)
Ito Makoto
Ohsawa Kenji
Sato Kazuhiro
Chambliss Alonzo
Chaudhuri Olik
Sonnenschein Nath & Rosenthal
Sony Corporation
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