Semiconductor package with heat dissipating structure

Details Semiconductor package with heat dissipating structure Semiconductor package with heat dissipating structure

2001-10-09

2002-10-29

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S705000, C257S706000, C257S707000, C257S796000

Reexamination Certificate

active

06472743

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package with a heat dissipating structure so as to improve heat dissipating efficiency thereof
BACKGROUND OF THE INVENTION
In the demand of high electricity and performance, a BGA (ball grid array) semi-conductor package correspondingly incorporates a greater quantity of I/O connections, and accommodates a plurality of array-arranged solder balls for electrically connecting a semiconductor chip to external devices, thereby making the semiconductor package become a mainstream product. However, in such a BGA semiconductor package, as the semiconductor chip is highly integrated due to the provision of the I/O connections in greater quantity, this accordingly results in more heat generated by operating such a semiconductor chip. Therefore, how to effectively dissipate the heat generated by the semiconductor chip is a main problem to be solved.
U.S. Pat. No. 5,977,626 discloses a semiconductor package having a heat sink for improving heat dissipating efficiency. As shown in
FIG. 10
, in the disclosed semi-conductor package
1
, a heat sink
10
is disposed on a substrate
12
, which is mounted with a chip
11
thereon. The heat sink
10
has a planar portion
100
, and a supporting portion
101
used to support the planar portion
100
above the chip
11
, wherein the planar portion
100
and the supporting portion
101
form a cavity
102
for receiving the chip
11
and gold wires
13
therein. The gold wires
13
are used to electrically connect the chip
11
to the substrate
12
in a manner as not to be in contact with the heat sink
10
. Moreover, the supporting region
101
a
is formed with a plurality of protrusions
101
a
for attaching the heat sink
10
to the substrate
12
via the protrusions
101
a.
Moreover, the heat sink
10
is made in a manner as to expose an upper surface
100
a
of the planar portion
100
to outside of an encapsulant
14
used for encapsulating the chip
11
, thereby making the exposed upper surface
100
a
in direct contact with the atmosphere, so as to effectively improve the heat dissipating efficiency for the foregoing semiconductor package
1
. Therefore, in a molding process for forming the encapsulant
14
, the heat sink
10
needs to be dimensioned for allowing the upper surface
100
a
of the planar portion
100
to abut a top wall of a molding cavity of an encapsulating mold (not shown), and the upper surface
100
a
can be exposed to the atmosphere after the encapsulant
14
is completely formed. However, due to dimensional inaccuracy in the fabrication of the substrate
12
and the heat sink
10
, if the heat sink
10
is made over-sized in height, the substrate
12
can be damaged by a stress from the heat sink
10
during the mold engagement. On the contrary, if the heat sink
10
is not sufficiently high, a gap is formed between the upper surface
100
a
of the heat sink
10
and the top wall of the molding cavity, thereby making a molding resin used for forming the encapsulant
14
flash over the upper surface
100
a
. This therefore detrimentally affects the heat dissipating efficiency of the heat sink
10
and appearance of the packaged product.
Moreover, the supporting portion
101
of the heat sink
10
is formed by stamping a planar metal piece, while this stamping process usually affects the planarity of the planar portion
100
of the heat sink
10
, and thus resin flash can easily occur on the upper surface
100
a
of the planar portion
100
. In a trend for fabricating low-profile semiconductor packages, a heat dissipating structure usually needs to be dimensioned to approximate 0.2 mm 0.2 mm or even thinner in thickness. Such a heat dissipating structure makes the planarity of its planar portion more easily affected during forming its supporting portion, and thus the resin flash problem is even more difficult to be eliminated.
Furthermore, the supporting portion
101
of the heat sink
10
is formed to extend outwardly and downwardly from a periphery of the planar portion
100
, thereby allowing the protrusions
101
a
in contact with the substrate
12
to be located outside a projection area of the planar portion
100
on the substrate
12
. As such, the substrate
12
needs to be dimensionally larger in surface area than the planar portion
100
so as to sufficiently accommodate the heat sink
10
thereon. This is then disadvantageous in dimensional miniaturization for the substrate
12
, and also generates restriction on the size of the chip
11
. Further, the protrusions
101
a
are attached to the substrate
12
by means of an adhesive, and thus are hardly to be precisely positioned. In the case of the protrusions
101
a
not accurately positioned on the substrate
12
, the heat sink
10
can then be entirely dislocated. This thereby results in damage to the product appearance, or causes short circuit due to the supporting portion
101
coming into contact with the gold wires
13
, which are used to electrically connect the chip
11
to the substrate
12
.
In addition, in order to attach the heat sink
10
to the substrate
12
via the supporting portion
101
, the substrate
12
needs to be sufficiently dimensioned for disposing the heat sink
10
on an area outside a wire-bonding area for accommodating the gold wires
13
, without coming into contact with the gold wires
13
on the substrate
12
. However, for a substrate having high density of gold wires disposed thereon for use with a highly integrated chip, there is often not possibly formed an sufficient area for mounting the supporting portion
101
outside the wire bonding area on the substrate. Similarly, a CSP (chip scale package) semiconductor package employs a substrate having an even smaller surface area, wherein the wire bonding area can only be formed between a die attaching area and a periphery of the substrate, thereby making the substrate not sufficient in area for accommodating the supporting portion
101
. Thus, the heat sink
10
disclosed in the U.S. Pat. No. 5,977,626 is not suitably used with the substrate having high density of the gold wires or with the substrate used in the CSP semiconductor package.
SUMMARY OF THE INVENTION
A primary objective of the present invention to provide a semiconductor package with a heat dissipating structure, in which the heat dissipating structure can be precisely positioned, and a substrate can be prevented from being damaged in a molding process, as well as, resin flash can be avoided occurring on an exposed side of the heat dissipating structure. Moreover, the heat dissipating structure is mounted on the substrate in a manner as not to affect the disposition of bonding wires on the substrate. Furthermore, an area for depositing the heat dissipating structure on the substrate can be significantly reduced; this therefore makes the heat dissipating structure suitably used with a substrate having high density of bonding wires or with a substrate used in a CSP semiconductor package, and makes a chip used in the semiconductor package not limited in size.
In accordance with the foregoing and other objectives, the present invention proposes a semiconductor package device with a heat dissipating structure, comprising a substrate having an upper side and an opposing lower side; at least one semiconductor chip mounted on the upper side of the substrate and electrically connected to the substrate; a heat dissipating structure having a plurality of solder balls implanted on the upper side of the substrate, and a heat sink attached to the solder balls, wherein the heat sink has an upper side and an opposing lower side, and a plurality of connection pads are formed on the lower side at corresponding positions for bonding the solder balls thereto, so as to make the heat sink supported by the solder balls and positioned above the semiconductor chip; and an encapsulant for encapsulating the semiconductor chip and the heat dissipating structure on the upper side of the substrate, wherein the upper sid

Affiliated with

Also associated with

Rating

Semiconductor package with heat dissipating structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor package with heat dissipating structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package with heat dissipating structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2973011