Semiconductor package with ground projections

Details Semiconductor package with ground projections Semiconductor package with ground projections

2001-12-12

2003-02-11

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S691000, C257S783000, C257S778000

Reexamination Certificate

active

06518660

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more particularly to a semiconductor package with a lid.
2. Description of Related Art
Wire bonding is commonly used for making electrical connections between an integrated circuit chip and a substrate. However, when the chip is intended for high electrical performance, a flip-chip bonding is often used instead of the wire bonding. In addition, when the chip needs extensive cooling, a lid is often attached on the back of the chip to improve heat removal from the chip.
FIGS. 1 and 2
show a conventional semiconductor package
100
with a lid
40
. Solder bumps
24
of a central processing unit (CPU) chip
20
are bonded by flip-chip bonding to corresponding substrate pads
16
on an upper surface
12
of a ceramic substrate
10
. The solder bumps
24
are external terminals of the CPU chip
20
, and the substrate pads
16
are electrically connected to external connection pins
30
which are on the bottom surface of the substrate
10
. The lid
40
is attached to the upper surface
12
of the substrate
10
to cover the CPU chip
20
. A flip-chip bonding part between the CPU chip
20
and the ceramic substrate
10
is filled with an encapsulant.
The lid
40
, which is made of a material having a good heat conductivity, such as Al or Cu, includes a cavity
48
for receiving the CPU chip
20
. In order to maximize the heat removal through the lid
40
, a thermal interface material
56
is interposed between an inner bottom surface of the cavity
48
of the lid
40
and the back surface of the CPU chip
20
. A nonconductive thermosetting silicon adhesive
54
is used for attaching the lid
40
to the upper surface of the ceramic substrate
10
. The nonconductive thermosetting silicon adhesive
54
is cured to complete the attachment between the lid
40
and the ceramic substrate
10
.
The electrically nonconductive thermosetting silicone adhesive
54
provides excellent adhesion between the ceramic substrate
10
and the lid
40
, and serves as a buffer for absorbing the stresses due to the difference of Coefficient of Thermal Expansion (CTE) between the ceramic substrate
10
and the lid
40
.
However, the above-described conventional semiconductor package
100
has a drawback in that this structure cannot sufficiently cope with Electromagnetic Interference (EMI). That is, after mounting the semiconductor package
100
on an electronic system, the semiconductor package
100
is often exposed to EMI generated by operation of the electronic system. This EMI may cause error in the operation of the CPU chip
20
or lower its performance.
In order to overcome the EMI problem, the metallic lid is grounded by replacing the conventional electrically nonconductive adhesive for attaching the lid to the substrate with an electrically conductive adhesive. For example, an electrically conductive thermosetting silicon adhesive or a solder may be used as the electrically conductive adhesive.
The electrically conductive thermosetting silicone adhesive performs the buffer function of reducing the stresses between the lid and the substrate. However, the electrically conductive thermosetting silicone adhesive does not produce good adhesion between the ceramic substrate and the lid. In contrast, the solder provides excellent adhesion between the That is, when solder is used, cracks or delaminations may be caused at the interface between the lid and the ceramic substrate due to thermal stresses. Such cracks can degrade the heat removal capacity of the package and further degrade electrical performance of the chip.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover over the chip; and one or more projections that electrically connect the lid to one or more ground patterns.
The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form ground patterns. The chip is bonded on the upper surface of the substrate. The chip can be electrically connected to the substrate pads by a wirebonding method or by a flipchip bonding method. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. In one embodiment, an electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections may be positioned at one or more of the four corners of a cavity that is formed between the substrate and the lid.
The semiconductor package further includes: external connection terminals formed on the lower surface of the substrate and electrically connected to the corresponding substrate pads; and a thermal interface material interposed between lid and the chip, the thermal interface material transmitting heat generated by the chip to the lid.


REFERENCES:
patent: 4410905 (1983-10-01), Grabbe
patent: 5258576 (1993-11-01), Newman et al.
patent: 5763824 (1998-06-01), King et al.
patent: 5901050 (1999-05-01), Imai
patent: 6084297 (2000-07-01), Brooks et al.
patent: 6349033 (2002-02-01), Dubin et al.
patent: 6351194 (2002-02-01), Takahashi et al.
patent: 6225694 (2002-05-01), Terui

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