Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2001-08-18
2003-04-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S667000, C257S787000, C257S737000, C257S738000, C257S687000, C438S784000, C438S112000, C438S124000, C438S126000, C438S127000, C264S272170
Reexamination Certificate
active
06555924
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabricating methods thereof, and more particularly, to a semiconductor package having a semiconductor chip mounted on a substrate and a fabricating method thereof
BACKGROUND OF INVENTION
A conventional BGA (ball grid array) semiconductor package employs an advanced technology, in which a substrate has a front side for disposing a semiconductor chip thereon and a back side for implanting a plurality of solder balls, so as to provide high density of I/O connections for electrically connecting the semiconductor package to an external printed circuit board.
A FCBGA (flip-chip ball grid array) semiconductor package is more improved than the conventional BGA semiconductor package, in that a semiconductor chip is mounted in the FCBGA semiconductor package in an upside-down manner that the chip has an upper side downwardly reflowed to a front side of a substrate by a plurality of solder bumps, while on a back side of the substrate there are implanted a plurality of solder balls for electrically connecting the semiconductor package to an external device, and accordingly the semiconductor package can be miniaturized in profile.
However, the solder bumps for mounting the chip on the substrate are disposed in a manner that a cavity is formed between the chip and the substrate. If the cavity is not filled with an insulative material, the chip and the substrate tend to be structurally damaged by a thermal stress generated from the difference in coefficient of thermal expansion (CTE) between the chip and the substrate during a temperature cycle in subsequent fabricating processes. Therefore, a flip chip underfill process, which fills the cavity between the chip and the substrate with the insulative material such as epoxy resin, is essential for fabricating the FCBGA semiconductor package, so as to enhance the structural strength for the semiconductor package.
Currently, U.S. Pat. Nos. 5,535,101 “Leadless Integrated Circuit Package” and U.S. Pat. No. 5,218,234 “Semiconductor Device with Controlled Spread Polymeric Underfill” have respectively disclosed a flip chip underfill technology; however, drawbacks have been found for the technology as follows. First, the flip chip underfill technology employs a capillary filling technique, which requires long filling time and tends to cause the formation of voids. Moreover, an ideal material used for filling the cavity between the chip and the substrate is commonly added with a solid filler for making the filling material have a similar CTE to that of the solder bumps, so as to protect the solder bumps from being damaged by a thermal stress. However, the addition of the solid filler significantly increases a viscosity of the filling material, which makes the filling material reduced in fluidity and the filling time further prolonged.
U.S. Pat. No. 6,038,136 discloses a simplified flip chip underfill technology, that is, a molded underfill technology in a molding process. As shown. in
FIG. 1
, a FCBGA semiconductor package
1
includes a substrate
10
having a front side
100
pre-formed with a chip bonding region
102
thereon for reflowing a semiconductor chip
12
on the chip bonding region
102
in a flip chip manner via a plurality of solder bumps
11
; while the substrate
10
has a back side
101
to be covered by a solder mask
16
in a manner that a plurality of solder pads
18
formed on the back side
101
are exposed for implanting a plurality of solder balls (not shown) thereon, and further, a specified molding compound
19
is used for encapsulating the chip
12
and the solder bumps
11
. The molding compound
19
is a low viscous epoxy resin containing a solid filler in 70-90%, wherein the solid filler consists of flue particles having small particle diameters within 0.01-0.05 mm such as silicon, quartz, etc.
The foregoing underfill technology is characterized in that the filling for a cavity between the chip
12
and the substrate
10
is implemented in the molding process. As shown in
FIG. 2
, after a filling material
19
(same as the molding compound
19
) is injected into a mold (not shown), excess air can escape through a plurality of air vents
17
connected to the outside for preventing the formation of voids. However, as the filling material
19
having high fluidity and a fine filler with a particle diameter smaller than 20 &mgr;m, and the air vents
17
about 40-50 &mgr;m in height are much higher than the filler's particle diameter, the low viscous filling material
19
can therefore freely leak out of the air vents
17
, making the filling material
19
seriously flash around the air vents
17
. In addition, the flashing material
19
can further flow through slots
104
at two sides of the substrate
10
to a bottom surface of the semiconductor package
1
, making the mold hard to be removed from the semiconductor package
1
due to the stickiness of the flashing material
19
; while the solder pads (not shown) formed on the back side
101
of the substrate
10
can also be easily contaminated by the flashing material
19
, and accordingly implantation of the solder balls on the solder pads is deteriorated in quality.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package and a fabricating method thereof, in which a flash preventing mechanism is formed at a front end of an air vent, for reducing an entry space of the air vent and accordingly making a molding compound flow slowly into the air vent, so as to help prevent the molding compound from flashing on a surface of a substrate. Moreover, flash of the molding compound can be prevented from occurring on a bottom surface of the semiconductor package in the invention, for allowing a mold to be easily removed after completing a molding process. In addition, the invention allows solder pads formed on the substrate to be free of flash, so as to assure the quality of an implantation process for implanting solder balls on the solder pads.
In accordance with the foregoing and other objectives, the present invention proposes a semiconductor package and a fabricating method thereof, comprising: a substrate having a front side and a back side is prepared, wherein the front side is pre-formed with a chip bonding region, and on the front side around the chip bonding region there are disposed a plurality of flash preventing mechanisms corresponding in position to entries of air vents in a mold; a semiconductor chip is mounted on the chip bonding region and electrically connected to the substrate; and an encapsulant is formed of a molding compound with high fluidity for encapsulating the chip and the flash preventing mechanisms, so that the fabrication for the semiconductor package is completed.
As the flash preventing mechanisms are disposed on the substrate corresponding in position to the entries of the air vents, in a molding process, flow of a molding compound can be impeded by the flash preventing mechanisms at the air vent entries for reducing the flow rate of the molding compound. Further, the flash preventing mechanisms occupy part of the entry spaces at the air vents, making the slower flowing molding compound able to rapid absorb heat from the mold and accordingly increase in viscosity, so as to effectively prevent flash of the molding compound from occurrence.
REFERENCES:
patent: 5450283 (1995-09-01), Lin et al.
patent: 5535101 (1996-07-01), Miles et al.
patent: 5672912 (1997-09-01), Aoki et al.
patent: 5844309 (1998-12-01), Takigawa et al.
patent: 6038136 (2000-03-01), Weber
patent: 6104095 (2000-08-01), Shin et al.
patent: 6246115 (2001-06-01), Tang et al.
patent: 6319450 (2001-11-01), Chua et al.
patent: 6329606 (2001-12-01), Freyman et al.
patent: 6369455 (2002-04-01), Ho et al.
patent: 6407461 (2002-06-01), Farquhar et al.
patent: 2002/0003308 (2002-01-01), Kim et al.
Chai Ting Ke
Pu Han Ping
Yuan Po Hauu
Corless Peter F.
Edwards & Angell LLP
Flynn Nathan J.
Greene Pershelle
Jensen Steven M.
LandOfFree
Semiconductor package with flash preventing mechanism and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package with flash preventing mechanism and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package with flash preventing mechanism and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3045596