Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-05-29
2004-03-09
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Reexamination Certificate
active
06703698
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package.
BACKGROUND OF THE INVENTION
BGA (ball grid array) is an advanced type of semiconductor packaging technology, which is characterized by the use of a substrate as a chip carrier whose front surface is used for mounting one or more semiconductor chips and whose back surface is provided with a plurality of array-arranged solder balls. During a SMT (surface mount technology) process, a BGA package can be mechanically bonded and electrically coupled to an external device such as a printed circuit board (PCB) by means of these solder balls.
Patents related to BGA technology include, for example, U.S. Pat. No. 5,851,337 entitled “METHOD OF CONNECTING TEHS ON PBGA AND MODIFIED CONNECTING STRUCTURE”. This patent is characterized by the use of a ground circuit for connecting a heat spreader to a substrate to help enhance grounding effect of a BGA package. One drawback to this patent, however, is that it is unsuitably used for packaging semiconductor chips having a great number of power and ground pads.
A conventional solution to the foregoing problem is depicted with reference to
FIGS. 1A and 1B
. As shown, an exemplified BGA package comprises: a substrate
100
, at least a semiconductor chip
110
, a power-connecting heat spreader
120
, a ground-connecting heat spreader
130
, a plurality of sets of bonding wires
141
,
142
,
143
, an encapsulation body
150
, and a plurality of array-arranged solder balls
160
.
The substrate
100
has a front surface
100
a
and a back surface
100
b
, and is formed with a plurality of electrically-conductive vias
101
a
,
101
b
,
101
c
at predetermined positions, including power vias
101
a
, ground vias
101
b
and I/O (input/output) vias
101
c
, which are adapted to penetrate through the substrate
100
.
The semiconductor chip
110
has an active surface
110
a
and an inactive surface
110
b
. The active surface
110
a
is formed with a plurality of bond pads
111
a
,
111
b
,
111
c
, including power pads
111
a,
ground pads
111
b
and I/O pads
111
e
. This active surface
110
a
of the semiconductor chip
110
is further formed with a power plane
112
a
and a ground plane
112
b
, wherein the power plane
112
a
is electrically connected to the power pads
111
a
by a first set of bonding wires
141
, and the ground plane
112
b
is electrically connected to the ground pads
111
b
by a second set of bonding wires
142
. Further, the I/O pads
111
c
are electrically connected by a third set of bonding wires
143
to the I/O vias
101
c
on the front surface
100
a
of the substrate
100
.
The power-connecting heat spreader
120
is integrally formed by a support portion
121
, an overhead portion
122
and a downward-extending portion
123
. The power-connecting heat spreader
120
is mounted over the substrate
100
to partly cover the semiconductor chip
110
, wherein the support portion
121
is electrically bonded to the power vias
101
a
of the substrate
100
, and the downward-extending portion
123
is electrically bonded to the power plane
112
a
on the semiconductor chip
110
, allowing the overhead portion
122
to be elevated in position above the semiconductor chip
110
by the support portion
121
and the downward-extending portion
123
. The power-connecting heat spreader
120
is used to connect power to the semiconductor chip
110
, and to dissipate heat generated by the semiconductor chip
110
during operation.
Similarly, the ground-connecting heat spreader
130
is composed of a support portion
131
, an overhead portion
132
and a downward-extending portion
133
. The ground-connecting heat spreader
130
is mounted over the substrate
100
to partly cover the semiconductor chip
110
, wherein the support portion
131
is electrically bonded to the ground vias
101
b
of the substrate
100
, and the downward-extending portion
133
is electrically bonded to the ground plane
112
b
on the semiconductor chip
110
, allowing the overhead portion
132
to be elevated in position above the semiconductor chip
110
by the support portion
131
and the downward-extending portion
133
. The ground-connecting heat spreader
130
is used to connect the semiconductor chip
110
to ground, and to dissipate heat generated by the semiconductor chip
110
during operation.
The encapsulation body
150
is formed to encapsulate the front surface
100
a
of the substrate
100
, the semiconductor chip
110
, the power-connecting heat spreader
120
, and the ground-connecting heat spreader
130
. In view of power transmission and grounding purposes, the power-connecting heat spreader
120
and the ground-connecting heat spreader
130
are preferably not exposed to outside of the encapsulation body
150
.
The array-arranged solder balls
160
are implanted on the back surface
100
b
of the substrate
100
, including a plurality of power balls
161
electrically connected to the power vias
101
a
, a plurality of ground balls
162
electrically connected to the ground vias
101
b
, and a plurality of I/O balls
163
electrically connected to the I/O vias
101
c.
By the above structure as illustrated in
FIG. 1A
, power can be externally supplied to the semiconductor chip
110
successively via the power balls
161
, the power vias
101
a
, the power-connecting heat spreader
120
, the power plane
112
a
, the bonding wires
141
, and the power pads
111
a
. Moreover, the semiconductor chip
110
can be connected to ground successively via the ground pads
111
b
, the bonding wires
142
, the ground plane
112
b
, the ground-connecting heat spreader
130
, the ground vias
101
b
, and the ground balls
162
. Further, the semiconductor chip
110
can transfer I/O signals via the I/O pads
111
c
, the bonding wires
143
, the I/O vias
101
e
, and the I/O balls
163
.
One drawback to the forgoing BGA package, however, is that, since the ground-connecting heat spreader
130
only covers part of the semiconductor chip
110
, it would not be able to provide good EMI (electromagnetic interference) shielding effect for the semiconductor chip
110
during operation.
Moreover, since both the power-connecting heat spreader
120
and the ground-connecting heat spreader
130
are completely enclosed by the encapsulation body
150
, they may not provide satisfactory heat-dissipation efficiency for the packaged semiconductor chip
110
.
SUMMARY OF THE INVENTION
An objective of this invention is to provide a semiconductor package with enhanced electrical and thermal performance, which provides good EMI (electromagnetic interference) shielding effect.
Another objective of this invention is to provide a semiconductor package with enhanced electrical and thermal performance, by which satisfactory heat-dissipation efficiency is achieved.
A further objective of this invention is to provide a semiconductor package with enhanced electrical and thermal performance, wherein the semiconductor package is cost-effectively fabricated.
In accordance with the above and other objectives, the present invention proposes a BGA semiconductor package and a method for fabricating the same.
The BGA semiconductor package of the invention comprises: a substrate having a front surface and a back surface opposed to the front surface; at least a chip having an active surface and an inactive surface opposed to the active surface, wherein the active surface is formed with a power plane and a ground plane, and the inactive surface is mounted on the front surface of the substrate; a power-connecting heat spreader adapted to entirely cover the chip, and electrically bonded to the front surface of the substrate and the power plane on the chip; a ground-connecting heat spreader positioned in elevation above the power-connecting heat spreader, and adapted to be electrically bonded to the front surface of the substrat
Huang Chien-Ping
Huang Chih-Ming
Corless Peter F.
Edwards & Angell LLP
Fahmy Wael
Favahani Dana
Jensen Steven M.
LandOfFree
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