Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2002-07-10
2004-09-14
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S737000, C257S784000, C257S787000
Reexamination Certificate
active
06791168
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packages and to methods of semiconductor packaging. More particularly, this invention relates to a semiconductor package having a die and a circuit side polymer layer on the die configured as a defect barrier. This invention also relates to a method for fabricating the package, and to systems incorporating the package.
BACKGROUND OF THE INVENTION
Different types of semiconductor packages have been developed recently with a smaller outline, and a higher pin count than conventional plastic or ceramic packages. These semiconductor packages are broadly referred to as BGA packages, chip scale packages or flip chip packages. One particular type of package is referred to as a board-on-chip (BOC) package.
Referring to
FIG. 1A
, a prior art BOC package
10
is illustrated. The BOC package
10
includes a substrate
12
, terminal contacts
14
on the substrate
12
, and a semiconductor die
16
attached to the substrate
12
in electrical communication with the terminal contacts
14
. Typically the substrate
12
comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin, and the terminal contacts
14
comprise solder balls in a dense area array, such as a ball grid array (BGA). In addition, the substrate
12
includes patterns of metal conductors
24
in electrical communication with the terminal contacts
14
. The conductors
24
typically fan out from bond pads
30
on the die
16
to the grid pattern of the terminal contacts
14
.
The BOC package
10
also includes adhesive members
26
, such as strips of adhesive tape, attaching a circuit side
32
of the die
16
to the substrate
12
. The substrate
12
includes a bonding opening
28
, and the die
16
is attached to the substrate
12
with the bond pads
30
on the circuit side
32
aligned with the bonding opening
28
. In addition, wires
22
are placed through the opening
28
, and are wire bonded to the bond pads
30
on the die
16
and to the conductors
24
on the substrate
12
. The BOC package
10
also includes a die encapsulant
18
encapsulating the die
16
, and a wire bond encapsulant
20
encapsulating the wires
22
. The die encapsulant
18
and the wire bond encapsulant
20
typically comprise a plastic material, such as a Novoloc based epoxy, formed using transfer molding process.
As shown in
FIG. 1B
, the adhesive members
26
do not completely cover the circuit side
32
of the die
16
. Accordingly, the die encapsulant
18
, and also the wire bond encapsulant
20
, can be in physical contact with exposed portions of the circuit side
32
of the die
16
.
One problem with the BOC package
10
is that stress defects often develop in the die
16
following the packaging process. As used herein a “stress defect” means the die
16
has an improper circuit structure that produces a present or future electrical failure in the operation of the die
16
or elements thereof.
One type of stress defect
38
is illustrated in FIG.
1
C. In this example, the die
16
includes interconnect conductors
34
on the circuit side
32
covered by a die passivation layer
36
. The interconnect conductors
34
are in electrical communication with the bond pads
30
, and with the integrated circuits (not shown) contained on the die
16
. The stress defects
38
can comprise cracks that form in the die passivation layer
36
and in the interconnect conductors
34
. These stress defects
38
can cause opens and shorts to occur in the interconnect conductors
34
. Stress defects
38
can also occur on other elements on the die
16
, such as on the bond pads
30
.
It has been theorized that the stress defects
38
are caused by fillers in the die encapsulant
18
, or in the wire bond encapsulant
20
that are in physical contact with the circuit side
32
of the die
16
. For example, epoxies used for the die encapsulant
18
and the wire bond encapsulant
20
often contain silicates, such as SiO
2
, that are used to adjust various physical or electrical characteristics of the epoxies. These fillers in physical contact with the circuits side
32
of the die
16
may be one source of stress defects
20
.
The present invention is directed to an improved semiconductor package having a stress defect barrier, and to a method for fabricating the package.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved semiconductor package, a wafer level method for fabricating the package, and systems incorporating the package, are provided.
In a first embodiment, the package has a board on chip (BOC) configuration. The package includes a BOC substrate having a pattern of conductors, a semiconductor die attached to the BOC substrate and wire bonded to the conductors, and a die encapsulant encapsulating the die and the substrate. The die includes die contacts, such as bond pads or redistribution contacts on a circuit side thereof, in electrical communication with integrated circuits on the die. The die also includes planarized wire bonding contacts on the die contacts, and a planarized polymer layer encapsulating the wire bonding contacts. The planarized polymer layer prevents physical contact between the die encapsulant and the integrated circuits on the circuit side of the die, and functions as a stress defect barrier between the integrated circuits and fillers contained in the die encapsulant.
In a second embodiment, a chip on board (COB) package includes a die having a planarized polymer layer and planarized wire bonding contacts. The die is back bonded and wire bonded to a COB substrate and a second die is attached to the die using an adhesive layer. The planarized polymer layer protects the die from fillers in the adhesive layer.
In a third embodiment, a stacked package includes the die having the planarized polymer layer and the planarized wire bonding contacts. In addition, the die is back bonded to a substantially similar die, mounted to a substrate and encapsulated in a die encapsulant.
In a fourth embodiment, a lead on chip (LOC) package includes a die having the planarized polymer layer and planarized wire bonding contacts. In addition, the die is attached and wire bonded to a segment of a lead on chip lead frame and encapsulated in a die encapsulant.
In each embodiment, the package can be used to construct systems such as modules, circuit boards, and systems in a package (SIP).
The method includes the step of providing a semiconductor substrate, such as a semiconductor wafer, containing a plurality of semiconductor dice having the die contacts on the circuit sides thereof. The method also includes the step of forming bumps on the die contacts, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form planarized wire bonding contacts. In addition, the method includes the step of singulating the dice from the semiconductor substrate such that each die includes a planarized polymer layer, and planarized wire bonding contacts encapsulated in the polymer layer.
The method also includes the steps of providing a lead frame containing a plurality of substrates, and attaching the dice to the substrates using one or more adhesive members. During the attaching step, the adhesive members are placed on the planarized polymer layers on the circuit sides of the dice. The attaching step is followed by the steps of wire bonding the planarized wire bonding contacts to conductors on the substrate, encapsulating the dice on the substrates, and singulating the substrates from the lead frame.
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Connell Mike
Jiang Tongbi
Gratton Stephen A.
Micro)n Technology, Inc.
Thai Luan
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