Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2000-10-27
2003-02-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S734000
Reexamination Certificate
active
06518667
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package, such as a flip chip package (FC-PKG) including a flip chip ball grid array (FC-BGA) and a method of manufacturing the semiconductor package. More specifically, the present invention relates to an inside electrode used in the semiconductor package and to a method of manufacturing the inside electrodes. It is to be noted throughout the instant specification that the inside electrodes are formed by balls and are also used in a prober for investigating a semiconductor device.
With the development of recent multimedia, a system using a silicon device tends to show high speed and high performance. However, it is becoming difficult more and more to sufficiently obtain the high performance of the device by packaging a silicon device and mounting the packaged device on a printed substrate only by a conventional method.
Specifically, even when the signal processing is carried out at a high speed, such a high-speed operation is restrained due to a delay of the signal propagation of a package and on a printed substrate and due to an error operation caused by a crosstalk noise.
Also, since the scale of LSI is increased and the performance thereof becomes higher, various difficult problems take place in the case of packaging and mounting LSI chips such that the number of I/O pins is increased. In addition, any other problems also take place such that the I/O pins become area arrays and heating from the chip is increased.
In such circumstances, the improvements of various mounting techniques are proposed as a new high-density mounting technique. As the techniques for supporting the improvements, the techniques of a chip size package (CSP) and a bear chip mount are largely developed. Particularly, in a technique of bonding a silicon chip (the chip is usually a silicon chip) to a surrounding material such as a substrate, flip chip mounting would be helpful. This is because such flip chip mounting makes it possible to reflow in a lump and to easily accomplish a desirable reliability. Moreover, there is a possibility that the flip chip mounting becomes particularly the inevitable technique in a next generation high-density package, etc.
Also, as the performance is increased and semiconductor devices are down-sized, it is required that a semiconductor package also becomes small in size and light in weight.
Herein, the flip chip mounting or connecting technique is helpful to connect a substrate and a chip in a lump by the use of protrusion electrodes (called bumps) on the chips. With this technique, it is possible to satisfy the requirements of increasing the number of pins of the I/O terminals (terminals of the inlet and outlet of circuit) and shortening the signal delayed time.
At any rate, a high-functional semiconductor device is manufactured by an electrolytic plating method, a vacuum vapor deposition method, and/or stud bump forming using a wire bonding method.
In these methods, particularly, the electrolytic plating method can simultaneously form all the bumps on a flat plane and is therefore considered to be relatively inexpensive as compared with other methods, and to be excellent in mass production.
According to recent reports about the formation of bumps, an aperture of about 100 &mgr;m is plated and the plating condition is discussed on the region of the size of at least about 120 &mgr;m. In addition, the content relates to mushroom-type bumps (see, Electronics Jisso Gakkai Shi (Journal of Japan Institute of Electronics Packaging), Vol. 1, No. 1, page 41, 1998).
Alternatively, recent attention has been made about a flip chip connection technique by a compressing technique. That is, the technique is a flip chip mounting technique of adhering IC to a circuit substrate by using hardening resin like film or paste and keeping the electric connection by the residual stress in the resin. This technique has a merit in that the productivity is high as compared with the prior art.
There is a technique of using an anisotropic conductive film (ACF) but since a technique of using an anisotropic conductive paste (ACP) and a non-conductive resin paste (NCP) in a driver IC of LCD, the material cost is low as compared with the case of the above-described film and a sticking device is unnecessary, the latter technique is rapidly beginning to be propagated.
The techniques are excellent in the accuracy in position-alignment and the reproducibility. However, such excellent accuracy is accomplished only on a two-dimensional package in connection with the hardness of a substrate and the relative deformation of a chip and a substrate. In other words, it is clear that such excellent accuracy can not be achieved on a high- density package of a three dimensional structure to which attention will be directed in the future. Particularly, no improvement can be achieved along the Z-axis direction in the conventional methods and, therefore, the above-described technique will be brought to a standstill.
It can be easily anticipated that the bump pitch is, at present, from 200 to 250 &mgr;m, but it becomes 100 &mgr;m or lower. Thus, the mounting technique practically suitable in such a case and the supply of packages thereof will be demanded. A report about the recent compression technique mentions the consideration of the damage on a substrate and a chip and also the accuracy of the warp of a substrate (see, Electronics Jisso Gijutsu (Electronics Packaging Technology), Vol. 15, No. 7, page 52,1999).
In addition, it is predicted as a future technique that the above-described three-dimensional stack type will be mainly investigated for the high-density package of a small size. Stacking bear chips might be a final form but in this case, the problems remain in the use of a semiconductor process and the protection of the chip itself. Thus, the practical use will be directed to stacking the packages, which will be accelerated.
In such a stream of the technique, proposal has been made about using micro balls as contact materials in a C
4
method (Controlled Collapsed Chip Connection/Flip Chip Attach), on mounting a chip and a substrate in a flip chip technique,
In a flip chip connected CSP of prior art, a semiconductor chip is electrically connected to one surface of a wiring substrate having an electrically conductive pattern formed on the surface of a ceramic or synthetic resin substrate via micro balls called flip chip balls (FC-Ball). In this event, the connected portions between the semiconductor chip and the wiring substrate are covered with an insulating resin. On the other hand, the other surface side of the wiring substrate is mounted on one surface of a substrate or an electric part via micro balls called ball grid array balls (BGA-Ball).
Such micro balls provide an effective and reliable means for mounting, particularly, the chip and the substrate when the C
4
method (Controlled Collapsed Chip Connection/Flip Chip Attach) or a technique of prior art similar to the C
4
method is used.
On the other hand, Nikkei Microdevices, January, 2000, page 148, reports that a burn in inspection apparatus has been given attention as a recent technical trend of the inspecting technique in semiconductor devices. In such an apparatus also, each terminal of a probe must be certainly brought into contact with each electrode on a wafer. Otherwise, a serious problem is caused to occur. This means that such an apparatus should have a total high-accurate construction for obtaining the function as the probe, in addition to the dimensional accuracy of parts used. In particular, it is very important that alignment along the Z-axis direction must be matched between the substrate and the chip both of which are connected to each other.
Practically, it is devised that collapse of posts is utilized to absorb a variation of heights of electrodes and a spring-attached probe is used as the terminal, etc. However, a sufficient accuracy can not obtained in this probe.
Now, as the method of obtaining spherical shaped particles or grains having a uniform particle s
Doi Yoshihiko
Ichida Akira
Mizukami Masahiko
Yoshida Hiroshi
Allied Material Corporation
Nguyen Thinh
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