Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-06-04
2004-12-28
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S618000, C257S701000, C257S702000
Reexamination Certificate
active
06835595
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor package, such as a wafer level CSP (Chip Size/Scale Package), using no wiring board (interposer), a semiconductor device, an electronic device, and a method for producing the semiconductor package; and particularly to a semiconductor package, a semiconductor device and an electronic device which can be produced with ease, and a method for producing the semiconductor package.
BACKGROUND ART
In recent years, a development of small-sized semiconductor devices has been promoted. With this development, attention is paid to the miniaturization of the packages of these semiconductor devices. For instance, a variety of semiconductor packages have been proposed in the August issue (1998) and February issue (1999) of Nikkei Micro-device. Among these packages, especially a wafer level CSP using a semiconductor package called CSP has a high effect on the miniaturization of a package and a reduction in costs. This CSP is a package resin-sealed together with a wafer.
FIG. 9
is a sectional view showing the structure of a conventional CSP. Incidentally,
FIG. 9
shows the condition that the above CSP will be mounted on a printed circuit board and the vertically positional relation between the parts explained hereinafter is reversed with respect to those of FIG.
9
.
In the conventional CSP, plural Al pads
52
are formed on a wafer
51
. Also a SiN layer
53
and a polyimide layer
54
which cover the Al pads
52
are formed on the entire surface of the wafer
51
. In the SiN layer
53
and the polyimide layer
54
, a via hole which reaches the Al pad
52
from the surface of the polyimide layer
54
is formed and a conductive layer
55
is embedded in the via hole. On the polyimide layer
54
, a rerouting layer
56
connected to the conductive layer
55
is formed. The rerouting layer
56
is formed of, for example, Cu. A sealing resin layer
57
coating the rerouting layer
56
is formed on the entire surface of the polyimide layer
54
. Inside the sealing resin layer
57
, a Cu post
58
which reaches the rerouting layer
56
from the surface of the sealing resin layer
57
is formed as a metal post. A barrier metal layer
59
is formed on the Cu post
58
and a solder ball
60
such as a solder is formed on the barrier metal layer
59
.
Next, a method for producing the conventional CSP as mentioned above will be explained.
FIGS. 10
(
a
) to (
e
) are sectional views showing the method for producing the conventional CSP in step order. Incidentally, the rerouting layer, the polyimide layer and the like are omitted in
FIGS. 10
(
a
) to (
e
).
Firstly, as shown in
FIG. 10
(
a
), a wafer
61
with a flat surface is prepared. As shown in
FIG. 10
(
b
), plural Cu posts
62
are formed on the wafer
61
by plating. Next, as shown in
FIG. 10
(
c
), all Cu posts
62
are resin-sealed such that they are encased to form a sealing resin layer
63
. Then, as shown in
FIG. 10
(
d
), the surface of the sealing resin layer
63
is polished to expose each Cu post
62
. Thereafter, as shown
FIG. 10
(
e
), a solder ball
64
such as a solder is mounted on each Cu post
62
.
The CSP as described above is thus formed. This CSP is made into a given size by dicing afterwards.
Since a semiconductor package is in general different from a printed circuit board or the like in thermal expansion coefficient, a stress based on the difference in thermal expansion coefficient focuses on a terminal of the semiconductor package. However, in the above-mentioned CSP, the stress is easily dispersed by making the cylindrical Cu post
62
have a large height.
However, in order to disperse the stress based on the difference in thermal expansion coefficient, it is necessary for a metal post, such as a Cu post, to have a height as large as about 100 &mgr;m from the rerouting layer. However, if a metal post having such a height is formed by plating, there is a problem that a remarkable long period of time is required. This further gives rise to the problems of increased production cost and a difficulty in control of the height of the metal post.
In light of such problems, the present invention has been made. It is an object of the present invention to provide a semiconductor package, a semiconductor device and an electronic device which make it possible to disperse a stress produced when the package is mounted on a printed circuit board or the like and which can be produced for a short time, and a method for producing the semiconductor package.
DISCLOSURE OF THE INVENTION
A semiconductor package according to the present invention comprises: an insulating layer formed on a wafer that is provided with an electrode; an opening portion made in a region conformable to the electrode in the insulating layer; a rerouting layer connected to the electrode through the opening portion; a sealing resin layer which seals the wafer, the insulating layer, and the rerouting layer; and a post penetrating through the sealing resin layer, a solder bump being formed on an upper surface of the post, wherein the post comprises: a resin projection portion formed on the insulating layer; and a conductive layer that coat at least an upper surface of the resin projection portion and are connected to the rerouting layer and the solder bump.
In the present invention, the post is provided with the resin projection portion wherein at least the upper surface thereof is coated with the conductive layer. Therefore, in the case that stress is generated in this post, the stress is dispersed mainly by the resin projection portion. For this reason, no thick plating layer is necessary for the post, so that the production process is shortened. Since the height of the post can be controlled by the height of the resin projection portion, the adjustment thereof is easy.
By making an area of the opening portion made in the sealing resin layer through which the post penetrates larger than that of the upper surface of the post, the contact area between the solder bump and the conductive layer can be made large. Therefore, the reliability of ensuring electric conduction and adhesive strength is improved. In this case, a boundary between the post and the sealing resin layer may be present outside the upper surface of the post as is viewed in plan.
In the case that the inner surface of the opening portion made in the sealing resin layer is inclined inwards to form a groove surrounding a periphery of the upper surface of the post and the boundary is divided by the groove, the flexibility of the deformation of the resin projection portion becomes large on the basis of resin-removal. Thus, the stress is still more easily dispersed.
In the case that at least one part of a periphery of the post is coated with the sealing resin layer and the sealing resin layer is formed to have such a thickness that its upper surface apart from the post is lower than the upper surface of the post, the flexibility of the deformation of the resin projection portion becomes large in the same way. Thus, the stress is still more easily dispersed.
Another semiconductor package according to the present invention comprises: a wafer that is provided with an electrode; a resin projection portion formed on the wafer; a conductive layer formed on the resin projection portion and connected to the electrode; a solder bump formed on the conductive layer above the resin projection portion; and a sealing resin layer which seals the wafer with the solder bump being exposed.
In this case, the stress acting from the solder bump to the resin projection portion can be still more uniformly dispersed if a position of the center of the solder bump is consistent with a position of the center of the resin projection portion as are viewed in plan.
A shape of the resin projection portion may be truncated cone.
The semiconductor device provided with any one of the above-mentioned semiconductor packages according to the present invention comprises an integrated circuit formed in the wafer.
The electronic device provided with this semiconductor device
Inaba Masatoshi
Kaizu Masahiro
Kurosaka Akihito
Masumoto Kenji
Masumoto Mutsumi
Berezny Nema
Fujikura Ltd.
Jr. Carl Whitehead
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