Semiconductor package including die interposed between...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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C257S691000, C257S778000, C257S779000, C438S661000, C174S263000

Reexamination Certificate

active

07394150

ABSTRACT:
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

REFERENCES:
patent: 5098626 (1992-03-01), Pas
patent: 5982041 (1999-11-01), Mitani et al.
patent: 6027957 (2000-02-01), Merritt et al.
patent: 6100580 (2000-08-01), Murakami et al.
patent: 6165819 (2000-12-01), Seki et al.
patent: 6486411 (2002-11-01), Miura et al.
patent: 6574861 (2003-06-01), Yang et al.
patent: 6580169 (2003-06-01), Sakuyama et al.
patent: 6613607 (2003-09-01), Janssen et al.
patent: 6670222 (2003-12-01), Brodsky
patent: 6744124 (2004-06-01), Chang et al.
patent: 6777788 (2004-08-01), Wan et al.
patent: 6777800 (2004-08-01), Madrid et al.
patent: 6949816 (2005-09-01), Brown et al.
patent: 2003/0051909 (2003-03-01), Kim et al.
patent: 2003/0052408 (2003-03-01), Quinones et al.
patent: 2003/0147333 (2003-08-01), Tokuda et al.
patent: 2004/0016995 (2004-01-01), Kuo et al.
patent: 2005/0212142 (2005-09-01), Miyazaki et al.
patent: 2005/0218426 (2005-10-01), Kobayashi et al.
patent: 2006/0110856 (2006-05-01), Kasem et al.
International Rectifier Application Note AN-1035 titled “DirectFET Technology” Version 6 dated Aug. 6, 2004 (cover page and pp. 3, 7).
International Rectifier Application Note AN-1059 titled “DirectFET Thermal Model and Rating Calculator” by Doug Butchers (4 pages).

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